IDT72P51339L6BBI8 IDT, Integrated Device Technology Inc, IDT72P51339L6BBI8 Datasheet - Page 21
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IDT72P51339L6BBI8
Manufacturer Part Number
IDT72P51339L6BBI8
Description
IC FLOW CTRL 36BIT 256-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT72P51339L6BB8.pdf
(87 pages)
Specifications of IDT72P51339L6BBI8
Configuration
Dual
Density
576Kb
Access Time (max)
3.7ns
Word Size
36b
Organization
2Kx36x8
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
BGA
Clock Freq (max)
166MHz
Supply Current
150mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72P51339L6BBI8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72P51339L6BBI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
(Commercial: V
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
FSYNC
ESYNC
PR
XIS
XIH
PPMS
PPMH
PAEHZ
PAFLZ
PAFHZ
FFHZ
FFLZ
EFLZ
EFHZ
FXO
EXO
SKEW1
SKEW2
SKEW3
SKEW4
(2)
(2)
(2)
(2)
(2)
(2)
(2)
WCLK to PAF Flag Bus to Low-Impedance
WCLK to PAF Flag Bus to High-Impedance
WCLK to Full Flag/Input Ready to High-Impedance
WCLK to Full Flag/Input Ready to Low-Impedance
RCLK to Empty Flag/Output Ready Flag to Low-Impedance
RCLK to Empty Flag/Output Ready Flag to High-Impedance
WCLK to PAF Bus Sync to Output
WCLK to PAF Bus Expansion to Output
RCLK to PAE Bus Sync to Output
RCLK to PAE Bus Expansion to Output
RCLK to Packet Ready Flag
SKEW
SKEW
SKEW
SKEW
Expansion Input Setup
Expansion Input Hold
Parallel Programming Setup
Parallel Programming Hold
DD
RCLK to PAE Flag Bus to High-Impedance
= 1.8V ± 0.10V, T
time between RCLK and WCLK for FF/IR and EF/OR
time between RCLK and WCLK for PAF and PAE
time between RCLK and WCLK for PAF[0:7] and PAE[0:7]
time between RCLK and WCLK for PR and EF/OR
A
Parameter
= 0°C to +70°C;Industrial: V
DD
= 1.8V ± 0.10V, T
21
Min.
IDT72P51339L5
IDT72P51349L5
IDT72P51359L5
IDT72P51369L5
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
1.5
0.5
15
5
5
5
5
5
Commercial
A
= -40°C to +85°C; JEDEC JESD8-A compliant)
Max.
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
—
—
—
—
—
—
—
—
Min.
IDT72P51339L6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
2.0
0.5
Com'l & Ind'l
15
IDT72P51349L6
IDT72P51359L6
IDT72P51369L6
6
6
6
6
5
COMMERCIAL AND INDUSTRIAL
Max.
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
(1)
—
—
—
—
—
—
—
—
TEMPERATURE RANGES
Unit
AUGUST 4, 2005
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns