IDT89HPES12NT3ZBBC IDT, Integrated Device Technology Inc, IDT89HPES12NT3ZBBC Datasheet - Page 2

• Manufacturer Part Number: IDT89HPES12NT3ZBBC
• Description: IC PCI SW 12LANE 3PORT 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES12NT3ZBBC

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES12NT3ZBBC

Product Description
the most efficient high-performance I/O connectivity solution for applica-
tions requiring high throughput, low latency, and simple board layout
with a minimum number of board layers. With support for non-trans-
parent bridging, the PES12NT3, as a standalone switch or as a chipset
with IDT PCIe System Interconnect Switches, enables multi-host and
intelligent I/O applications requiring inter-domain communication. The
PES12NT3 provides 48 Gbps (6 GBps) of aggregated, full-duplex
switching capacity through 12 integrated serial lanes, using proven and
robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in
both directions and is fully compliant with PCI Express Base specifica-
tion 1.0a.
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 1.0a. The PES12NT3 can operate either as a store and
forward or cut-through switch depending on the packet size and is
designed to switch memory and I/O transactions. It supports eight Traffic
Classes (TCs) and one Virtual Channel (VC) with sophisticated resource
management. This includes round robin port arbitration, guaranteeing
IDT 89HPES12NT3 Data Sheet
Utilizing standard PCI Express interconnect, the PES12NT3 provides
The PES12NT3 is based on a flexible and efficient layered architec-
◆
◆
◆
◆
◆
◆
◆
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates twelve 2.5 Gbps embedded full duplex SerDes,
– Upstream port can be dynamically swapped with non-trans-
– Internal end-to-end parity protection on all TLPs ensures data
– Supports ECRC pass-through in transparent and non-trans-
– Supports Hot-Swap
– Supports PCI Power Management Interface specification,
– Unused SerDes are disabled
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
– Slave interface provides full access to all software-visible
– Master interface provides connection for an optional serial
– Master and slave interfaces may be tied together so the switch
Highly Integrated Solution
Reliability, Availability, and Serviceability (RAS) Features
Power Management
Testability and Debug Features
Two SMBus Interfaces
Eight General Purpose Input/Output pins
Packaged in 19x19mm 324-ball BGA with 1mm ball spacing
queueing
8B/10B encoder/decoder (no separate transceivers needed)
parent downstream port to support failover applications
integrity even in systems that do not implement end-to-end
CRC (ECRC)
parent ports
Revision 1.1 (PCI-PM)
registers by an external SMBus master
EEPROM used for initialization
can act as both master and slave
2 of 29
bandwidth allocation and/or latency for critical traffic classes in applica-
tions such as high throughput 10 GbE I/Os, SATA controllers, and Fibre
Channel HBAs.
Switch Configuration
lanes. Each of the three ports is statically allocated 4 lanes with ports
labeled as A, B and C. Port A is the upstream port, port B is the trans-
parent downstream port, and port C is the non-transparent downstream
port.
PES12NT3 port is capable of independently negotiating to a x4, x2 or x1
width. Thus, the PES12NT3 may be used in virtually any three port
switch configuration (e.g., {x4, x4, x4}, {x4, x2, x2}, {x4, x2, x1}, etc.).
The PES12NT3 supports static lane reversal. For example, lane
reversal for upstream port A may be configured by asserting the PCI
Express Port A Lane Reverse (PEALREV) input signal or through serial
EEPROM or SMBus initialization. Lane reversal for ports B and C may
be enabled via a configuration space register, serial EEPROM, or the
SMBus.
The PES12NT3 is a three port switch that contains 12 PCI Express
During link training, link width is automatically negotiated. Each
February 19, 2009