IDT89HPES16T4ZHBC IDT, Integrated Device Technology Inc, IDT89HPES16T4ZHBC Datasheet - Page 6
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IDT89HPES16T4ZHBC
Manufacturer Part Number
IDT89HPES16T4ZHBC
Description
IC PCI SW 16LANE 4PORT 484-CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT89HPES16T4ZHBC.pdf
(31 pages)
Specifications of IDT89HPES16T4ZHBC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
89HPES16T4ZHBC
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Part Number:
IDT89HPES16T4ZHBC
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Quantity:
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IDT 89HPES16T4 Data Sheet
MSMBSMODE
SWMODE[2:0]
RSTHALT
GPIO[11]
GPIO[12]
Signal
Signal
CCLKDS
CCLKUS
PERSTN
GPIO[8]
Type
Type
I/O
I/O
I/O
I
I
I
I
I
I
Table 4 General Purpose I/O Pins (Part 2 of 2)
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P1RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 1
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P6RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 6
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P7RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 7
Common Clock Downstream. When the CCLKDS pin is asserted, it indi-
cates that a common clock is being used between the downstream device
and the downstream port.
Common Clock Upstream. When the CCLKUS pin is asserted, it indi-
cates that a common clock is being used between the upstream device and
the upstream port.
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
Fundamental Reset. Assertion of this signal resets all logic inside
PES16T4 and initiates a PCI Express fundamental reset.
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES16T4 executes the reset procedure and remains in a reset state
with the Master and Slave SMBuses active. This allows software to read
and write registers internal to the device before normal device operation
begins. The device exits the reset state when the RSTHALT bit is cleared in
the SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the PES16T4 switch
operating mode. These pins should be static and not change after the
negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
Table 5 System Pins
6 of 31
Name/Description
Name/Description
March 25, 2008