IDT89HPES16T4ZHBC IDT, Integrated Device Technology Inc, IDT89HPES16T4ZHBC Datasheet - Page 4

• Manufacturer Part Number: IDT89HPES16T4ZHBC
• Description: IC PCI SW 16LANE 4PORT 484-CABGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES16T4ZHBC

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES16T4ZHBC

Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES16T4 Data Sheet
The following tables list the functions of the pins provided on the PES16T4. Some of the functions listed may be multiplexed onto the same pin.
Note: In the PES16T4, the three downstream ports are labeled port 1, port 6, and port 7.
PEREFCLKN[2:1]
PEREFCLKP[2:1]
P01MERGEN
P67MERGEN
PE0RN[3:0]
PE1RN[3:0]
PE6RN[3:0]
PE7RN[3:0]
PE0RP[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE1RP[3:0]
PE1TP[3:0]
PE1TN[3:0]
PE6RP[3:0]
PE6TP[3:0]
PE6TN[3:0]
PE7RP[3:0]
PE7TP[3:0]
PE7TN[3:0]
REFCLKM
Signal
Type
O
O
O
O
I
I
I
I
I
I
I
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1. When port 0 is merged with port 1, these signals become
port 0 receive pairs for lanes 4 through 7.
PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 1. When port 0 is merged with port 1, these signals
become port 0 transmit pairs for lanes 4 through 7.
PCI Express Port 6 Serial Data Receive. Differential PCI Express receive
pairs for port 6.
PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 6.
PCI Express Port 7 Serial Data Receive. Differential PCI Express receive
pairs for port 7. When port 6 is merged with port 7, these signals become
port 6 receive pairs for lanes 4 through 7.
PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 7. When port 6 is merged with port 7, these signals
become port 6 transmit pairs for lanes 4 through 7.
Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low
internally via a 251K ohm resistor.
When this pin is low, port 0 is merged with port 1 to form a single x8 port.
The Serdes lanes associated with port 1 become lanes 4 through 7 of port
0. When this pin is high, port 0 and port 1 are not merged, and each oper-
ates as a single x4 port.
Port 6 and 7 Merge. P67MERGEN is an active low signal. It is pulled low
internally via a 251K ohm resistor.
When this pin is low, port 6 is merged with port 7 to form a single x8 port.
The Serdes lanes associated with port 7 become lanes 4 through 7 of port
6. When this pin is high, port 6 and port 7 are not merged, and each oper-
ates as a single x4 port.
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 2 PCI Express Interface Pins
4 of 31
Name/Description
March 25, 2008