ISL62884CIRTZ Intersil, ISL62884CIRTZ Datasheet - Page 22

• Manufacturer Part Number: ISL62884CIRTZ
• Description: IC REG PWM SGL PHASE 28TQFN
• Manufacturer: Intersil

Specifications of ISL62884CIRTZ

• Applications: Controller, Intel IMVP-6
• Voltage - Input: 4.5 ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 ~ 1.5 V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Layout Guidelines
Table 5 shows the layout considerations. The designators
refer to the reference designs shown in Figure 22.
Phase Node Minimize phase node copper area. Don’t let the phase node copper overlap with/getting close to other sensitive
DPRSLPVR No special consideration.
CLK_EN#
DPRSTP# No special consideration.
VID0~6
PGOOD
VR_ON
ISUM+
NAME
UGATE
PHASE
RBIAS
ISUM-
LGATE
COMP
BOOT
VSEN
VCCP
VSSP
GND
VDD
RTN
VIN
VW
FB
Create analog ground plane underneath the controller and the analog signal processing components. Don’t let the
power ground plane overlap with the analog ground plane. Avoid noisy planes/traces (e.g.: phase node) from
crossing over/overlapping with the analog plane.
No special consideration.
No special consideration.
Place the R
plane.
Place capacitor (C
Place compensator components (C
Place the VSEN/RTN filter (C
A capacitor (C
Place the current sensing circuit in general proximity of the controller.
Place C
Place NTC thermistors R
The power stage sends a pair of VSUM+ and VSUM- signals to the controller. Run these two signal traces in parallel
fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads.
Route R
of inductor L1.
If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to
the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of
the inductor. The following drawings show the two preferred ways of routing current sensing traces.
A capacitor (C
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE trace to the high-side MOSFET (Q2 and Q8) source pins
instead of general phase node copper.
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing VSSP to the low-side MOSFET (Q3) source pins instead of general
power ground plane for better performance.
A capacitor (C
No special consideration.
No special consideration.
traces. Cut the power ground plane to avoid overlapping with phase node copper.
Minimize the loop consisting of input capacitor, high-side MOSFETs and low-side MOSFETs (e.g.: C
82
63
very close to the controller.
BIAS
to the phase-node side pad of inductor L1. Route the other current sensing trace to the output side pad
16
17
22
22
resistor (R
) decouples it to GND. Place it in close proximity of the controller.
) decouples it to GND. Place it in close proximity of the controller.
) decouples it to GND. Place it in close proximity of the controller.
4
) across VW and COMP in close proximity of the controller.
42
16
next to inductor (L1) so it senses the inductor temperature correctly.
) in general proximity of the controller. Low impedance connection to the analog ground
12
TABLE 5. LAYOUT CONSIDERATIONS
, C
13
3
, C
) in close proximity of the controller for good decoupling.
SENSING TRACES
5
, C
VIAS
INDUCTOR
CURRENT-
ISL62884C
6
LAYOUT CONSIDERATION
R
7
, R
11
, R
10
and C
SENSING TRACES
INDUCTOR
CURRENT-
11
) in general proximity of the controller.
27
, C
33
March 16, 2010
, Q2, Q3).
FN7591.0