L6756D STMicroelectronics, L6756D Datasheet - Page 31

• Manufacturer Part Number: L6756D
• Description: IC CTLR 2/3/4PH BUCK 40-VFQFPN
• Manufacturer: STMicroelectronics

Specifications of L6756D

• Applications: Controller, Intel VR10, VR11, VR11.1
• Voltage - Input: 12V
• Number Of Outputs: 4
• Voltage - Output: 0.3 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Output Voltage: 3 V
• Input Voltage: - 0.3 V to + 15 V
• Switching Frequency: 185 KHz to 215 KHz
• Operating Temperature Range: - 40 C to + 150 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L6756D
9.1
Figure 15. Control loop bode diagram and fine tuning
To obtain the desired shape an R
implementation. A zero at ω
integrator minimizes the static error while placing the zero ω
C resonance assures a simple -20 dB/dec shape of the gain.
In fact, considering the usual value for the output filter, the LC resonance results to be at
frequency lower than the above reported zero.
Compensation network can be simply designed placing ω
over frequency ω
1/10 th of the switching frequency F
Compensation network guidelines
The compensation network design assures to having system response according to the
cross-over frequency selected and to the output filter considered: it is anyway possible to
further fine-tune the compensation network modifying the bandwidth in order to get the best
response of the system as follow (See
Having the fastest compensation network gives not the confidence to satisfy the
requirements of the load: the inductor still limits the maximum dI/dt that the system can
afford. In fact, when a load transient is applied, the best that the controller can do is to
“saturate” the duty cycle to its maximum (d
dV/dt is then limited by the inductor charge / discharge time and by the output capacitance.
In particular, the most limiting transition corresponds to the load-removal since the inductor
results being discharged only by V
appliance).
R
C
F
F
=
=
–
–
–
R
--------------------------------- -
------------------- -
C
FB
R
O
F
Increase R
Decrease R
Increase C
system phase margin.
⋅
V
⋅
ΔV
IN
L
OSC
T
⋅
as desired obtaining (always considering that ω
10
----- - ω
6
F
F
F
⋅
to increase the system bandwidth accordingly;
to move ω
to decrease the system bandwidth accordingly;
T
⋅
------------------------------------------ -
N
F
=1/R
⋅
(
R
F
LL
F
F
L
to low frequencies increasing as a consequence the
-C
OUT
C
+
SW
F
ESR
F
is then introduced together with an integrator. This
series network is considered for the Z
):
(while it is charged by V
Figure
)
MAX
15):
) or minimum (0) value. The output voltage
System control loop compensation
F
= ω
F
in correspondence with the L-
LC
IN
-V
and imposing the cross-
T
OUT
might be not higher than
during a load
F
(s)
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