FAN5018BMTCX Fairchild Semiconductor, FAN5018BMTCX Datasheet - Page 22

• Manufacturer Part Number: FAN5018BMTCX
• Description: IC CTRLR DC-DC MULTIPH 28TSSOP
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5018BMTCX

• Applications: Controller, High-Current, Implementing Low-Voltage CPU Core Power Circuits
• Voltage - Input: 12V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 3.5 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

C
FAN5018B
where K=4.6
Using eight 820µF A1-Polys with a typical ESR of 8m
each yields CX = 6.56µF with an RX = 1.0m
check should be made to ensure that the ESL of the bulk
capacitors (LX) is low enough to limit the initial high-
frequency transient spike. This can be tested using:
In this example, L
tors, which satisfies this limitation. If the L
bulk capacitor bank is too large, the number of MLC capaci-
tors must be increased.
Note: For this multi-mode control technique, “all-
ceramic” designs can be used as long as the conditions of
Equations 11, 12 and 13 are satisfied.
Power MOSFETs
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches
per phase. The main selection parameters for the power
MOSFETs are V
The minimum gate drive voltage (the supply voltage to the
FAN5009) dictates whether standard threshold or logic-level
threshold MOSFETs must be used. With V
logic-level threshold MOSFETs (V
recommended. The maximum output current I
the R
MOSFETs. With the FAN5018B, currents are balanced
between phases, thus the current in each low-side MOSFET
is the output current divided by the total number of
MOSFETs (n
the following expression shows the total power being
dissipated in each synchronous MOSFET in terms of the
ripple current per phase (I
current (I
Knowing the maximum output current being designed for
and the maximum allowed power dissipation, one can find
the required R
MOSFETs up to an ambient temperature of 50ºC, a safe limit
for P
22
C
P
L
L
X
SF
X
X
X
(
(
MIN
MAX
=
≤
≤
SF
DS(ON)
(
)
)
220
1
C
≥
≤
is 1W–1.5W at 125ºC junction temperature. Thus,
−
Z
⎛
⎜
⎝
O
3
D
×
3
μ
):
×
)
650
×
4
R
F
requirement for the low-side (synchronous)
×
1
SF
6 .
650
2
O
⎡
⎢
⎢
⎣
DS(ON)
3 .
×
⎛
⎜ ⎜
⎝
2
nH
). With conduction losses being dominant,
m
×
(
n
GS(TH)
nH
I
1
SF
Ω
O
(
X
1
3 .
×
3 .
×
×
is 375pH for the eight A1-Poly capaci-
⎞
⎟ ⎟
⎠
60
m
2
m
1
for the MOSFET. For D-PAK
250
+
Ω
5 .
Ω
A
, Q
12
V
)
)
1
mV
2
2
R
G
−
×
×
=
) and average total output
, C
1
220
⎛ ×
⎜ ⎜
⎝
5 .
372
n
ISS
V
n
μ
SF
×
, C
F
I
pH
⎛
⎜
⎜
⎝
R
GS(TH)
⎞
⎟
⎠
⎞
⎟ ⎟
⎠
RSS
1
=
2
+
⎤
⎥
⎥
⎦
. 6
×
⎛
⎜
⎝
150
45
and R
R
< 2.5V) are
DS
mF
GATE
X
μ
(
SF
Ω
s
of the chosen
250
DS(ON)
×
. One last
)
O
1
~10V,
5 .
determines
mV
V
×
.
×
3
650
Ω
×
(14)
(15)
,
4
6 .
nH
×
1
3 .
m
Ω
for our example (65A maximum), we find R
(per MOSFET) < 8.7m
temperature of about 125ºC, so we need to make sure we
account for this when making this selection. For our exam-
ple, we selected two lower side MOSFETs at 8.6m
room temperature, which gives 8.4m
Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio
of the feedback to input needs to be small (less than 10% is
recommended), to prevent accidental turn-on of the synchro-
nous MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off
should not exceed the non-overlap dead time of the
MOSFET driver (40ns typical for the FAN5009). The
output impedance of the driver is about 2
MOSFET input gate resistances are about 1
gate capacitance should be less than 6000pF. Since there are
two MOSFETs in parallel, we should limit the input capaci-
tance for each synchronous MOSFET to 3000pF.
The high-side (main) MOSFET has to be able to handle two
main power dissipation components; conduction and switch-
ing losses. The switching loss is related to the amount of
time it takes for the main MOSFET to turn on and off, and to
the current and voltage that are being switched. Basing the
switching speed on the rise and fall time of the gate driver
impedance and MOSFET input capacitance, the following
expression provides an approximate value for the switching
loss per main MOSFET, where n
main MOSFETs:
Here, R
and about 1
making R
main MOSFET. Adding more main MOSFETs (nMF) does
not significantly help the switching loss per MOSFET since
the additional gate capacitance slows down switching. The
best way to reduce switching loss is to use lower gate capac-
itance devices.
The conduction loss of the main MOSFET is given by the
following, where R
MOSFET:
P
P
S
⎞
⎟
⎠
C
(
2
(
MF
MF
−
)
1
)
⎞
⎟
⎟
⎠
= 2
=
G
−
D
220
is the total gate resistance (2
G
×
×
Ω
= 3
⎡
⎢
⎢
⎣
μ
f
for typical high speed switching MOSFETs,
⎛
⎜ ⎜
⎝
SW
F
Ω
n
I
MF
=
) and CISS is the input capacitance of the
O
×
23
V
DS(MF)
⎞
⎟ ⎟
⎠
2
9 .
CC
n
+
mF
Ω
MF
×
12
1
. This R
I
×
O
is the ON-resistance of the
⎛ ×
⎜ ⎜
⎝
×
n
n
R
MF
G
MF
I
DS(SF)
R
×
PRODUCT SPECIFICATION
⎞
⎟ ⎟
⎠
is the total number of
n
2
Ω
⎤
⎥
⎥
⎦
MF
n
Ω
×
at high temperature.
is also at a junction
REV. 1.0.0 Jul/15/05
for the FAN5009
R
Ω
×
DS
C
and the typical
Ω
(
DS(SF)
MF
ISS
–2
)
Ω
, so a total
Ω
each at
(17)
(16)