ISL8103IRZ Intersil, ISL8103IRZ Datasheet - Page 21

• Manufacturer Part Number: ISL8103IRZ
• Description: IC CTRLR PWM BUCK 3PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL8103IRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 12.6 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in “Load-Line (Droop) Regulation” on page 12,
there are two distinct methods for achieving these goals.
Compensating the Load-Line Regulated Converter
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
FIGURE 19. COMPENSATION CONFIGURATION FOR
FIGURE 18. TIME CONSTANT MISMATCH BEHAVIOR
ΔV
1
R
LOAD-LINE REGULATED ISL8103 CIRCUIT
1
R
2
C
2
C
(Optional)
1
21
2
and C
COMP
VDIFF
FB
1
.
ΔV
ΔI
2
ISL8103
V
I
TRAN
OUT
ISL8103
yields a solution that is always stable with very close to ideal
transient performance.
The feedback resistor, R
outlined in “Load-Line (Droop) Regulation” on page 12.
Select a target bandwidth for the compensated system, F
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of
F
frequency. For each of the following three, there is a
separate set of equations for the compensation components.
In Equation 28, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent series resistance of
the bulk output filter capacitance; and V
peak sawtooth signal amplitude as described in the
“Electrical Specifications” on page 5.
Once selected, the compensation values in Equations 28
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R
value of R
oscilloscope until no further improvement is noted. Normally,
C
Equations 28 unless some performance issue is noted.
The optional capacitor C
noise away from the PWM comparator (see Figure 19). Keep
a position available for C
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
Case 1:
Case 2:
Case 3:
0
1
to the L-C double pole frequency and the ESR zero
will not need adjustment. Keep the value of C
2
while observing the transient performance on an
R
C
---------------------------
2π
R
C
---------------------------
2π
2
1
2
1
⋅
=
=
1
⋅
=
=
L C
1
R
------------------------------------------------------------------------------- -
(
2π
L C
R
⋅
------------------------------------------------ -
2π V
1
⋅
1
⋅
)
V
--------------------------------------------------------------- -
2
⋅
≤
⋅
2
1
0.66 V
2
2π F
----------------------------------------------------------- -
OSC
>
⋅
F
R
C
F
, has already been chosen as
, is sometimes needed to bypass
, and be prepared to install a high
OSC
F
0
F
0
2
2
2
0
⋅
0
>
<
0.66 V
=
=
⋅
⋅
⋅
-------------------------------- -
2π C ESR
0.66 V
V
-------------------------------- -
2π C ESR
0
0.66 V
(
⋅
R
-------------------------------------------------------------- -
2π V
2π
OSC
⋅
IN
R
0.66 V
V
1
⋅
⋅
⋅
1
)
⋅
OSC
⋅
⋅
2
⋅
1
1
⋅
IN
2π F
-----------------------------------------------
⋅
⋅
f
⋅
0.66 V
⋅
OSC
0
⋅
IN
R
F
IN
2
⋅
2
0
1
⋅
IN
. Slowly increase the
PP
⋅
⋅
⋅
L C
0
⋅
L C
⋅
R
L C
⋅
ESR
⋅
⋅
is the peak-to-
IN
V
1
⋅
OSC
⋅
⋅
F
ESR
⋅
0
⋅
1
⋅
C
L
from
July 21, 2008
L
(EQ. 28)
FN9246.1
0
.