ISL8103IRZ Intersil, ISL8103IRZ Datasheet - Page 19

• Manufacturer Part Number: ISL8103IRZ
• Description: IC CTRLR PWM BUCK 3PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL8103IRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 12.6 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 6x6 QFN package is approximately 4W at
room temperature. See “Layout Considerations” on page 25
for thermal transfer improvement suggestions.
When designing the ISL8103 into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P
integrated driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 20
and 21, respectively.
In Equations 20 and 21, P
power loss and P
loss; the gate charge (Q
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I
quiescent current with no load at both drive outputs; N
and N
phase, respectively; N
phases. The I
controller without capacitive load and is typically 75mW at
300kHz.
P
I
DR
P
P
Qg_TOT
Qg_TOT
Qg_Q1
Qg_Q2
=
Q2
⎛
⎝
3
-- - Q
2
, due to the gate charge of MOSFETs and the
•
are the number of upper and lower MOSFETs per
=
=
=
3
-- - Q
2
Q
P
G1
Qg_Q1
G2
⋅
Q*
•
G1
VCC product is the quiescent power of the
⋅
N
PVCC F
Qg_Q2
Q1
⋅
+
PVCC F
P
+
PHASE
Qg_Q2
Q
⋅
G1
G2
is the total lower gate drive power
Qg_Q1
SW
⋅
and Q
•
19
SW
N
+
⋅
is the number of active
Q2
N
I
Q
Q2
⋅
⎞
⎠
is the total upper gate drive
⋅
N
G2
VCC
•
Q1
⋅
N
N
) is defined at the
PHASE
Q
PHASE
⋅
N
is the driver total
PHASE
•
F
SW
+
I
(EQ. 21)
(EQ. 20)
Q
Q1
ISL8103
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P
P
power will be dissipated by the external gate resistors (R
and R
the MOSFETs. Figures 15 and 16 show the typical upper
and lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P
estimated as shown in Equation 22.
P
DR_UP
P
DR_LOW
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
P
P
R
DR_UP
DR
PVCC
BOOT
EXT1
G2
=
, and in the boot strap diode, P
) and the internal gate resistors (R
PHASE
P
=
=
=
=
R
DR_UP
R
LO2
⎛
⎜
⎝
BOOT
P
---------------------
⎛
⎜
⎝
R
HI2
R
--------------------------------------
R
--------------------------------------
R
R
Qg_Q1
G1
LO1
HI1
HI1
HI2
3
+
R
+
R
DR_UP
+
+
R
-------------
N
HI1
HI2
P
R
R
GI1
Q1
DR_LOW
LGATE
EXT1
EXT2
UGATE
, the lower drive path resistance,
+
+
--------------------------------------- -
R
--------------------------------------- -
R
+
LO1
LO2
R
P
R
G2
BOOT
R
R
R
EXT2
G
G1
+
+
LO1
LO2
DR
G
R
R
R
C
EXT1
EXT2
, can be roughly
GI2
GD
BOOT
+
R
C
=
C
GI1
(
GD
GS
I
C
R
Q
⎞
⎟
⎠
⎞
⎟
⎠
GS
GI1
G2
•
•
•
. The rest of the
S
VCC
P
---------------------
P
---------------------
+
Qg_Q1
S
Qg_Q2
and R
R
-------------
N
3
2
D
GI2
Q2
)
D
July 21, 2008
Q2
C
(EQ. 22)
GI2
FN9246.1
DS
Q1
C
DS
) of
G1