ISL8105AIBZ-T Intersil, ISL8105AIBZ-T Datasheet

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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 All other trademarks mentioned are the property of their respective owners. ISL8105, ISL8105A April 15, 2010 FN6306.5 Output Voltage Range IN (+5V to +12V) DS(ON) | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007, 2010. All Rights Reserved ...

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... ISL8105IBZ* 8105 IBZ ISL8105IRZ* 5IRZ ISL8105ACRZ* 05AZ ISL8105AIBZ* 8105 AIBZ ISL8105AIRZ* 5AIZ ISL8105AEVAL1Z Evaluation Board *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...

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Block Diagram SAMPLE AND HOLD 21.5μA TO BGATE/BSOC FB 5V INT. 0.4V 20μA COMP/EN POR AND SOFT-START + - OC COMPARATOR 5V INT. PWM COMPARATOR 0. ERROR AMP DIS + - OSCILLATOR FIXED 300kHZ OR 600kHz ...

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... Package +150°C BOOT . . . . . . . . . . . . . . . .15V Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Bias Voltage, V Ambient Temperature Range ISL8105C, ISL8105AC . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL8105I, ISL8105AI .-40°C to +85°C Junction Temperature Range .-40°C to +125°C ...

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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL TGATE Source Resistance R TG-SRCl ...

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LX (SOIC Pin 8, DFN Pin 10) Connect this pin to the source of the top-side MOSFET and the drain of the bottom-side MOSFET used as the sink for the TGATE driver and to monitor the voltage drop ...

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V OVER-CHARGED OUT V V PRE-BIASED PRE-BIASED OUT OUT V NORMAL V NORMAL OUT OUT FIGURE 3. SOFT-START WITH PRE-BIAS to 10.2ms for the delay and OCP sample and 6.8ms for the soft-start ramp. Figure 3 shows ...

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BGATE > 425ns BGATE = 425ns BGATE < 425ns BGATE << 425ns FIGURE 4. BGATE PULSE STRETCHING The overcurrent function will trip at a peak inductor current (I ) determined by Equation 1: PEAK × × BSOC ...

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INTERNAL SOFT-START RAMP V OUT 6.8ms FIGURE 5. OVERCURRENT RETRY OPERATION Output Voltage Selection The output voltage can be programmed to any level between the 0.6V internal reference the V ISL8105, ISL8105A can run at ...

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So based on typical circuits, a 20V maximum good starting assumption; the user should verify the IN ringing in their particular application. Another consideration for high V is duty cycle. Very low IN duty ...

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BOOT C BOOT LX ISL8105 +V BIAS BGATE/BSOC V BIAS C VBIAS GND GND FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES Minimize the loop from any pulldown transistor connected to COMP/EN pin to reduce antenna effect. Provide local ...

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HF ripple component at the COMP pin and minimizing resultant duty cycle jitter ------------------- - = ---------- - ...

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However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure ...

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... For information on the Application circuit, including a complete Bill-of-Materials and circuit board description, can be found in Application Note AN1258. http://www.intersil.com/data/an/AN1258.pdf . The boot capacitor, BIAS , develops a floating supply voltage referenced to the ) each time the lower MOSFET voltage in the system ...

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... Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2 TERMINAL TIP MILLIMETERS MIN ...

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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...