ISL8105AIBZ-T Intersil, ISL8105AIBZ-T Datasheet - Page 9

• Manufacturer Part Number: ISL8105AIBZ-T
• Description: IC PWM CTRLR BUCK 1PHASE 8-SOIC
• Manufacturer: Intersil

Specifications of ISL8105AIBZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 660kHz
• Duty Cycle: 100%
• Voltage - Supply: 6.5 V ~ 14.4 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 660kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Voltage Selection
The output voltage can be programmed to any level between
the 0.6V internal reference, up to the V
ISL8105, ISL8105A can run at near 100% duty cycle at zero
load, but the r
limit it to something less as the load current increases. In
addition, the OCP (if enabled) will also limit the maximum
effective duty cycle.
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage, and feed it
back to the inverting input of the error amp. See “Typical
Application Diagram” on page 2 for more detail; R
upper resistor; R
lower one. The recommended value for R
(±1% for accuracy) and then R
to Equations 2 and 3. Since R
circuit (see “Feedback Compensation” on page 11), it is
often easier to change R
voltage; that way the compensation calculations do not need
to be repeated. If V
open. Output voltages less than 0.6V are not available.
Input Voltage Considerations
The “Typical Application Diagram” on page 2 shows a
standard configuration where V
12V (±20%); in each case, the gate drivers use the V
voltage for BGATE and BOOT/TGATE. In addition, V
allowed to work anywhere from 6.5V up to the 14.4V
maximum. The V
NOT allowed for long-term reliability reasons, but
transitions through it to voltages above 6.5V are acceptable.
R
V
OUT
0
=
----------------------------------
V
FIGURE 5. OVERCURRENT RETRY OPERATION
=
R
OUT
0.6V
1
•
0.6V
–
V
t0
OUT
DS(ON)
0.6V
•
(
------------------------- -
R
OFFSET
BIAS
1
R
OUT
+
0
6.8ms
R
of the top-side MOSFET will effectively
0
range between 5.5V and 6.5V is
INTERNAL SOFT-START RAMP
)
= 0.6V, then R
OFFSET
(shortened to R
1
9
OFFSET
BIAS
is part of the compensation
t1
t1
to change the output
is either 5V (±10%) or
OFFSET
BIAS
is chosen according
6.8ms
6.8ms
0
1
below) is the
is 1kΩ to 5kΩ
supply. The
can be left
1
0ms TO 6.8ms
is the
ISL8105, ISL8105A
BIAS
t2
t2
BIAS
(EQ. 2)
(EQ. 3)
is
There is an internal 5V regulator for bias; it turns on between
5.5 and 6.5V. Some of the delay after POR is there to allow a
typical power supply to ramp-up past 6.5V before the
soft-start ramps begins. This prevents a disturbance on the
output, due to the internal regulator turning on or off. If the
transition is slow (not a step change), the disturbance should
be minimal. So while the recommendation is to not have the
output enabled during the transition through this region, it
may be acceptable. The user should monitor the output for
their application to see if there is any problem.
The V
as V
sources, such as outputs of other regulators. If V
powers up first, and the V
initialization is done, then the soft-start will not be able to
ramp the output, and the output will later follow part of the
V
change the sequencing of the supplies, or use the
COMP/EN pin to disable V
Figure 6 shows a simple sequencer for this situation. If
V
will turn Q
When V
determines when Q
release the shut-down. If V
turning Q
soon as V
nominal, so a wide variety of NFET's or NPN's or even some
logic IC's can be used as Q1 or Q
leakage when off (open-drain or open-collector) so as not to
interfere with the COMP output. Q
near the COMP/EN pin.
The V
0.6V reference). It can be as high as 20V (for V
below V
voltage.
The first consideration for high V
voltage of 36V. The V
voltage - the diode drop) + any ringing (or other transients)
on the BOOT pin must be less than 36V. If V
limits V
The second consideration for high V
(BOOT - V
BOOT = V
IN
BIAS
ramp when it is applied. If this is not desired, then
BIAS
IN
IN
powers up first, Q
BIAS
IN
IN
to the top-side MOSFET can share the same supply
range can be as low as ~1V (for V
2
but can also run off a separate supply or other
2
). There are some restrictions for running high V
BIAS
IN
BIAS
turns on, the resistor divider R
off; so the ISL8105, ISL8105A will start-up as
on, keeping the ISL8105, ISL8105A in shutdown.
+ ringing to 16V.
+ V
FIGURE 6. SEQUENCER CIRCUIT
) voltage; this must be less than 24V. Since
comes up. The V
BIAS
R
R
1
2
V
1
IN
+ ringing, that reduces to (V
turns on, which will turn off Q
IN
(as seen on LX) + V
1
R
Q
V
IN
will be off, and R
3
BIAS
OUT
1
IN
is not present by the time the
powers up first, Q
until both supplies are ready.
TO COMP/EN
DISABLE
IN
Q
2
2
2
; but Q
is the maximum BOOT
IN
should also be placed
is the maximum
1
trip point is 0.4V
2
OUT
3
and R
must be low
pulling to V
BIAS
IN
as low as the
is 20V, that
1
OUT
IN
BIAS
2
will be on,
(boot
2
+ ringing)
April 15, 2010
and
just
FN6306.5
BIAS
IN