ISL8105AIBZ-T Intersil, ISL8105AIBZ-T Datasheet - Page 8

• Manufacturer Part Number: ISL8105AIBZ-T
• Description: IC PWM CTRLR BUCK 1PHASE 8-SOIC
• Manufacturer: Intersil

Specifications of ISL8105AIBZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 660kHz
• Duty Cycle: 100%
• Voltage - Supply: 6.5 V ~ 14.4 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 660kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The overcurrent function will trip at a peak inductor current
(I
where I
typical). The scale factor of 2 doubles the trip point of the
MOSFET voltage drop, compared to the setting on the
R
due to the MOSFET's r
current and temperature). To avoid overcurrent tripping in
the normal operating load range, find the R
from Equation 1 with:
For an equation for the ripple current, see “Output Inductor
Selection” on page 13.
The range of allowable voltages detected (2*I
is 0mV to 475mV; but the practical range for typical
I
PEAK
1. The maximum r
2. The minimum I
3. Determine I
PEAK
BSOC
temperature
ΔI
) determined by Equation 1:
=
is the output inductor ripple current.
BSOC
resistor. The OC trip point varies in a system mainly
2
----------------------------------------------------- -
FIGURE 4. BGATE PULSE STRETCHING
×
I
BSOC
is the internal BSOC current source (21.5µA
r
DS ON
PEAK
(
×
BSOC
DS(ON)
R
)
for I
BSOC
DS(ON)
BGATE < 425ns
BGATE << 425ns
BGATE > 425ns
BGATE = 425ns
from the specification table
PEAK
at the highest junction
8
variations (over process,
> I
OUT(MAX)
BSOC
+
BSOC
(
--------- -
ΔI
2
resistor
)
*R
ISL8105, ISL8105A
, where
BSOC
(EQ. 1)
)
MOSFETs is typically in the 20mV to 120mV ballpark
(500Ω to 3000Ω). If the voltage drop across R
too low, that can cause almost continuous OCP tripping and
retry. It would also be very sensitive to system noise and
inrush current spikes, so it should be avoided. The maximum
usable setting is around 0.2V across R
the MOSFET); values above that might disable the
protection. Any voltage drop across R
than 0.3V (0.6V MOSFET trip point) will disable the OCP.
The preferred method to disable OCP is simply to remove
the resistor, which will be detected as no OCP.
Note that conditions during power-up or during a retry may
look different than normal operation. During power-up in a
12V system, the IC starts operation just above 4V; if the
supply ramp is slow, the soft-start ramp might be over well
before 12V is reached. So with bottom-side gate drive
voltages, the r
power-up, effectively lowering the OCP trip. In addition, the
ripple current will likely be different at lower input voltage.
Another factor is the digital nature of the soft-start ramp. On
each discrete voltage step, there is in effect a small load
transient, and a current spike to charge the output
capacitors. The height of the current spike is not controlled; it
is affected by the step size of the output, the value of the
output capacitors, as well as the IC error amp compensation.
So it is possible to trip the overcurrent with inrush current, in
addition to the normal load and ripple considerations.
Figure 5 shows the output response during a retry of an
output shorted to GND. At time t
turned off, due to sensing an overcurrent condition. There
are two internal soft-start delay cycles (t
MOSFETs to cool down, to keep the average power
dissipation in retry at an acceptable level. At time t
output starts a normal soft-start cycle, and the output tries to
ramp. If the short is still applied, and the current reaches the
BSOC trip point any time during soft-start ramp period, the
output will shut off and return to time t
cycle. Thus, the retry period is two dummy soft-start cycles
plus one variable one (which depends on how long it takes to
trip the sensor each time). Figure 5 also shows an example
where the output gets about half-way up before shutting
down; therefore, the retry (or hiccup) time will be around
17ms. The minimum should be nominally 13.6ms and the
maximum 20.4ms. If the short condition is finally removed,
the output should ramp up normally on the next t
Starting up into a shorted load looks the same as a retry into
that same shorted load. In both cases, OCP is always
enabled during soft-start; once it trips, it will go into retry
(hiccup) mode. The retry cycle will always have two dummy
time-outs, plus whatever fraction of the real soft-start time
passes before the detection and shutoff; at that point, the
logic immediately starts a new two dummy cycle time-out.
DS(ON)
of the MOSFETs will be higher during
0
, the output has been
BSOC
0
BSOC
1
for another delay
and t
that is greater
(0.4V across
BSOC
2
) to allow the
2
2
cycle.
April 15, 2010
, the
is set
FN6306.5