ISL8103 INTERSIL [Intersil Corporation], ISL8103 Datasheet
ISL8103
Related parts for ISL8103
ISL8103 Summary of contents
Page 1
... An optional droop function is also implemented and can be disabled for applications having less stringent output voltage variation requirements or experiencing less severe step loads. A unique feature of the ISL8103 is the combined use of both DCR and r current sensing. Load line voltage DS(ON) positioning and overcurrent protection are accomplished ...
Page 2
... Pinout 3PH 2PH DAC REF OFST VCC COMP FB VDIFF RGND 2 ISL8103 ISL8103 (6x6 QFN) TOP VIEW GND BOOT1 29 PHASE1 28 PHASE2 27 UGATE2 26 BOOT2 ISEN2 25 PVCC2 24 23 LGATE2 ...
Page 3
... ISUM IREF RGND VSEN x1 x1 VDIFF UVP OVP OVP +150mV x 0.82 REF1 DAC REF0 DAC REF E/A FB COMP OFST OFFSET 3 ISL8103 OCSET PGOOD OVP 100µA OC +1V SOFT-START AND FAULT LOGIC 0.2V CLOCK AND SAWTOOTH GENERATOR ∑ PWM1 ∑ PWM2 ∑ PWM3 CHANNEL 1 CURRENT ...
Page 4
... Typical Application - ISL8103 FB VDIFF VSEN RGND 3PH +5V 2PH VCC OFST FS DAC ISL8103 REF REF1 REF0 OVP PGOOD +12V GND ENLL IREF DROOP OCSET ICOMP 4 ISL8103 +12V COMP PVCC1 BOOT1 UGATE1 PHASE1 ISEN1 LGATE1 +12V PVCC2 BOOT2 UGATE2 PHASE2 ISEN2 LGATE2 +12V ...
Page 5
... VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature (ISL8103CRZ 0°C to 70°C Ambient Temperature (ISL8103IRZ .-40°C to 85°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...
Page 6
... Upper Drive Source Resistance Upper Drive Sink Resistance Lower Drive Source Resistance Lower Drive Sink Resistance OVER TEMPERATURE SHUTDOWN Thermal Shutdown Setpoint (Note 3) Thermal Recovery Setpoint (Note 3) NOTE: 3. Parameter magnitude guaranteed by design. Not 100% tested. 6 ISL8103 TEST CONDITIONS R = 10K to ground 100pF 10K to ground 100pF, Load = ± ...
Page 7
... RUGATE t Q1 CHANNEL1 Q2 DAC Q3 CHANNEL2 Q4 ISL8103 Q5 CHANNEL3 Q6 ENLL (Pin 37) This pin is a threshold sensitive (approximately 0.66V) enable input for the controller. Held low, this pin disables controller operation. Pulled high, the pin enables the controller for operation. FS (Pin 36) A resistor, placed from FS to ground, will set the switching frequency ...
Page 8
... These pins make up the 2-bit input that selects the fixed DAC reference voltage. These pins respond to TTL logic thresholds. The ISL8103 decodes these inputs to establish one of four fixed reference voltages; see “Table 1” for correspondence between REF0 and REF1 inputs and reference voltage settings ...
Page 9
... The ISL8103 controller helps simplify implementation by integrating vital functions and requiring minimal output components. The block diagram on page 3 provides a top level view of multi-phase power conversion using the ISL8103 controller ...
Page 10
... PWM Operation The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL8103 is three. One switching cycle is defined as the time between the internal PWM1 pulse termination signals. The pulse termination signal is the internally generated clock signal that triggers the falling edge of PWM1 ...
Page 11
... The ISL8103 senses the channel load current by sampling the voltage across the lower MOSFET simply SEN Figure 5. A ground-referenced operational amplifier, internal to the ISL8103, is connected to the PHASE node through a , after the SW resistor, R the voltage drop across the r while it is conducting. The resulting current into the ISEN pin ...
Page 12
... This dependence of output voltage on load current is often termed “droop” or “load line” regulation. The Droop is an optional feature in the ISL8103. It can be enabled by connecting ICOMP pin to DROOP pin as shown in Figure 6. To disable it, connect the DROOP pin to IREF pin ...
Page 13
... R COMP temperature. Output Voltage Offset Programming The ISL8103 allows the designer to accurately adjust the offset voltage by connecting a resistor, R (EQ. 7) pin to VCC or GND. When R and VCC, the voltage across it is regulated to 1.5V. This ⋅ ...
Page 14
... FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE conduction Gate Drive Voltage Versatility DS(ON) The ISL8103 provides the user flexibility in choosing the gate drive voltage for efficiency optimization. The controller ties the upper and lower drive rails together. Simply applying a voltage from 12V on PVCC sets both gate drive rail voltages simultaneously ...
Page 15
... ENLL bias. The ISL8103 also has the ability to start up into a pre- 1.40kΩ charged output as shown in Figure 12, without causing any unnecessary disturbance. The FB pin is monitored during ...
Page 16
... The LGATE outputs remain high until VDIFF falls to within the overvoltage limits explained above. The ISL8103 will continue to protect the load in this fashion as long as the overvoltage condition recurs. Once an overvoltage condition ends the ISL8103 continues PGOOD normal operation and PGOOD returns high ...
Page 17
... Open Sense Line Protection In the case that either of the remote sense lines, VSEN or GND, become open, the ISL8103 is designed to detect this and shut down the controller. This event is detected by monitoring the voltage on the IREF pin, which is a local version of V sensed at the outputs of the inductors ...
Page 18
... QFN package is approximately 4W at room temperature. See Layout Considerations paragraph for thermal transfer improvement suggestions. and the 1 When designing the ISL8103 into an application UP,1 recommended that the following calculation is used to ensure safe operation at the desired frequency for the (EQ ...
Page 19
... EXT1 Current Balancing Component Selection The ISL8103 senses the channel load current by sampling the voltage across the lower MOSFET r Figure 17. The ISEN pins are denoted ISEN1, ISEN2, and ISEN3. The resistors connected between these pins and the D respective phase nodes determine the gains in the channel ...
Page 20
... Load Line Regulation Component Selection (DCR Current Sensing) For accurate load line regulation, the ISL8103 senses the total output current by detecting the voltage across the output inductor DCR of each channel (As described in the Load Line Regulation section). As Figure 7 illustrates, an ...
Page 21
... Figure 21 highlights the voltage-mode control loop for a 2 ⋅ ⋅ synchronous-rectified buck converter, applicable, with a (EQ. 28) small number of adjustments, to the multi-phase ISL8103 circuit. The output voltage (V voltage, VREF, level. The error amplifier output (COMP pin ⋅ ⋅ voltage) is compared with the oscillator (OSC) modified saw- ...
Page 22
... C ESR ⋅ ⋅ 2π The compensation network consists of the error amplifier (internal to the ISL8103) and the external R components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F ; typically 0 margin (better than 45 degrees). Phase margin is the difference ...
Page 23
... Because it has a low bandwidth compared to the switching frequency, the output filter limits the system 23 ISL8103 transient response. The output capacitors must supply or sink load current while the current in the output inductors 1 -------------------------------------------- - increases or decreases to meet the demand ...
Page 24
... The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to 24 ISL8103 handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases. ...
Page 25
... EMI pick-up also important to place current sense components close to their respective pins on the ISL8103, including the RISEN resistors, RS, RCOMP, CCOMP. For proper current sharing route three separate symmetrical as possible traces from the corresponding phase node for each RISEN ...
Page 26
... REF0 OVP PGOOD +12V GND ENLL IREF DROOP ICOMP OCSET ISUM R COMP R OCSET C COMP FIGURE 27. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS 26 ISL8103 LOCATE CLOSE TO IC (MINIMIZE CONNECTION PATH) +12V C HF01 COMP PVCC1 C HF1 BOOT1 C BOOT1 UGATE1 PHASE1 ISEN1 R ISEN1 LGATE1 ...
Page 27
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 27 ISL8103 L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJD-2 ISSUE C) ...