ISL8105AIBZ-T Intersil, ISL8105AIBZ-T Datasheet - Page 6

• Manufacturer Part Number: ISL8105AIBZ-T
• Description: IC PWM CTRLR BUCK 1PHASE 8-SOIC
• Manufacturer: Intersil

Specifications of ISL8105AIBZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 660kHz
• Duty Cycle: 100%
• Voltage - Supply: 6.5 V ~ 14.4 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 660kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LX (SOIC Pin 8, DFN Pin 10)
Connect this pin to the source of the top-side MOSFET and
the drain of the bottom-side MOSFET. It is used as the sink
for the TGATE driver and to monitor the voltage drop across
the bottom-side MOSFET for overcurrent protection. This pin
is also monitored by the adaptive shoot-through protection
circuitry to determine when the top-side MOSFET has turned
off.
N/C (DFN Only; Pin3, Pin 7)
These two pins in the DFN package are No Connect.
Functional Description
Initialization (POR and OCP Sampling)
Figure 1 shows a start-up waveform of ISL8105. The
Power-ON-Reset (POR) function continually monitors the
bias voltage at the VBIAS pin. Once the rising POR
threshold is exceeded 4V (V
initiates the Overcurrent Protection (OCP) sample and hold
operation (while COMP/EN is ~1V). When the sampling is
complete, V
If the COMP/EN pin is held low during power-up, the
initialization will be delayed until the COMP/EN is released
and its voltage rises above the V
Figure 2 shows a typical power-up sequence in more detail.
The initialization starts at t
V
COMP/EN will be pulled up by an internal 20µA current
source, but the timing will not begin until the COMP/EN
exceeds the V
capacitance of the disabling device, as well as the
compensation capacitors, will determine how quickly the
20µA current source will charge the COMP/EN pin. With
typical values, it should add a small delay compared to the
soft-start times. The COMP/EN will continue to ramp to ~1V.
From t
VBIAS pin to exceed 6.5V (if rising up towards 12V), so that
the internal bias regulator can turn on cleanly. At the same
POR
~4V POR
, or the COMP/EN pin is released (after POR). The
1
FIGURE 1. POR AND SOFT-START OPERATION
, there is a nominal 6.8ms delay, which allows the
OUT
DISABLE
begins the soft-start ramp.
trip point (at t
0
, when either V
POR
6
DISABLE
nominal), the POR function
1
). The external
trip point.
BIAS
rises above
V
COMP/EN
ISL8105, ISL8105A
V
V
OUT
BIAS
time, the BGATE/BSOC pin is initialized by disabling the
BGATE driver and drawing BSOC (nominal 21.5µA) through
R
trip point. At t
sample and hold operation (0ms to 3.4ms nominal; the
longer time occurs with the higher overcurrent setting). The
sample and hold uses a digital counter and DAC to save the
voltage, so the stored value does not degrade, for as long as
the V
(OCP)” on page 7 for more details on the equations and
variables. Upon the completion of sample and hold at t
soft-start operation is initiated, and the output voltage ramps
up between t
Soft-Start and Pre-Biased Outputs
Functionally, the soft-start internally ramps the reference on
the non-inverting terminal of the error amp from 0V to 0.6V in
a nominal 6.8ms. The output voltage will thus follow the
ramp, from zero to final value, in the same 6.8ms (the actual
ramp seen on the V
due to some initialization timing, between t
The ramp is created digitally, so there will be 64 small
discrete steps. There is no simple way to change this ramp
rate externally, and it is the same for either frequency
version of the IC (300kHz or 600kHz).
After an initialization period (t
(COMP/EN pin) is enabled, and begins to regulate the
converter's output voltage during soft-start. The oscillator's
triangular waveform is compared to the ramping error
amplifier voltage. This generates LX pulses of increasing
width that charge the output capacitors. When the internally
generated soft-start voltage exceeds the reference voltage
(0.6V), the soft-start is complete and the output should be in
regulation at the expected voltage. This method provides a
rapid and controlled output voltage rise; there is no large
inrush current charging the output capacitors. The entire
start-up sequence from POR typically takes up to 17ms; up
BSOC
FIGURE 2. BGATE/BSOC AND SOFT-START OPERATION
BIAS
t0 t1
. This sets up a voltage that will represent the BSOC
is above V
3.4ms
4
2
COMP/EN
BGATE/BSOC
, there is a variable time period for the OCP
and t
5
OUT
3.4ms
.
POR
will be less than the nominal time),
. See “Overcurrent Protection
t2 t3
3
to t
t4
0ms to 3.4ms
BGATE
STARTS
SWITCHING
4
), the error amplifier
3
and t
t5
4
V
).
April 15, 2010
OUT
FN6306.5
3
, the