ISL8120IRZ Intersil, ISL8120IRZ Datasheet - Page 31

• Manufacturer Part Number: ISL8120IRZ
• Description: IC CTRLR PWM 2PHASE W/DVR 32-QFN
• Manufacturer: Intersil

Specifications of ISL8120IRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1.5MHz
• Duty Cycle: 90%
• Voltage - Supply: 3 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1.5MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET datasheet; I
total quiescent current with no load at drive outputs; N
N
To keep the IC within its operating temperature range, an
external power resistor could be used in series with VIN pin
to bring the heat out of the IC, or and external LDO could be
used when necessary.
P
P
P
P
P
R
Q2
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
DR
DR_UP
DR_LOW
Qg_Q1
Qg_Q2
EXT2
PVCC
are number of upper and lower MOSFETs, respectively.
=
PVCC
P
=
=
=
DR_UP
=
R
=
Q
-------------------------------------- - F
Q
-------------------------------------- - F
⎛
⎜
⎝
G1
--------------------------------------
R
G1
G2
⎛
⎜
⎝
R
R
HI1
--------------------------------------
R
LO2
+
R
HI2
V
V
R
HI2
•
•
+
LO1
R
-------------
R
GS1
GS2
N
HI1
PVCC
PVCC
+
P
GI1
HI1
Q1
R
DR_LOW
R
+
GND
HI2
LGATE
EXT1
R
UGATE
PHASE
BOOT
EXT2
2
2
•
•
G1
+
+
--------------------------------------- -
R
SW
SW
31
and Q
R
LO1
--------------------------------------- -
R
R
G2
R
LO2
•
•
EXT2
G
R
G1
N
N
+
G
LO1
R
Q1
Q2
GS1
G2
R
R
+
LO2
C
GI2
GD
Q_VIN
R
EXT1
R
C
=
) is defined at a
C
GI1
GD
EXT2
and V
GS
R
C
GS
G2
⎞
⎟
⎠
S
•
⎞
⎟
⎠
is the driver’s
+
P
---------------------
•
S
GS2
R
-------------
Qg_Q1
N
P
---------------------
GI2
D
Q2
2
Qg_Q2
D
) in the
2
Q2
C
Q1
DS
C
Q1
(EQ. 8)
DS
and
ISL8120
Oscillator
The Oscillator is a sawtooth waveform, providing for leading
edge modulation with 350ns minimum dead time. The
oscillator (Sawtooth) waveform has a DC offset of 1.0V.
Each channel’s peak-to-peak of the ramp amplitude is set
proportional the voltage applied to its corresponding EN/FF
pin. See “Voltage Feed-forward” on page 23.
Frequency Synchronization and Phase Lock Loop
The FSYNC pin has two primary capabilities: fixed frequency
operation and synchronized frequency operation. By tying a
resistor (R
frequency can be set at any frequency between 150kHz and
1.5MHz. The frequency setting curve shown in Figure 21 is
provided to assist in selecting the correct value for R
By connecting the FSYNC pin to an external square pulse
waveform (such as the CLOCK signal, typically 50% duty
cycle from another ISL8120), the ISL8120 will synchronize
its switching frequency to the fundamental frequency of the
input waveform. The maximum voltage to the FSYNC pin is
VCC + 0.3V. The Frequency Synchronization feature will
synchronize the leading edge of CLKOUT signal with the
falling edge of Channel 1’s PWM clock signal. The CLKOUT
is not available until the PLL locks.
The locking time is typically 130µs for F
EN/VFF1 is released for a soft-start cycle until the FSYNC
stabilized and the PLL is in locking. The PLL circuits control
only EN/FF1, and control Channel 2’s soft-start instead of
EN/FF2. Therefore, it is recommended to connect all EN/FF
pins together in multiphase configuration.
The loss of a synchronization signal for 13 clock cycles
causes the IC to be disabled until the PLL returns locking, at
which point a soft-start cycle is initiated and normal
operation resumes. Holding FSYNC low will disable the IC.
1,600
1,400
1,200
1,000
800
600
400
200
FIGURE 21. R
0
FSYNC
20 40 60 80 100 120 140 160 180 200 220 240 260
) to GND from the FSYNC pin, the switching
FS
vs SWITCHING FREQUENCY
R_FS (kΩ )
SW
= 500kHz.
March 20, 2009
FSYNC
FN6641.0
.