ISL8120IRZ Intersil, ISL8120IRZ Datasheet - Page 23

• Manufacturer Part Number: ISL8120IRZ
• Description: IC CTRLR PWM 2PHASE W/DVR 32-QFN
• Manufacturer: Intersil

Specifications of ISL8120IRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1.5MHz
• Duty Cycle: 90%
• Voltage - Supply: 3 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1.5MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Initialization
Initially, the ISL8120 Power-On Reset (POR) circuits
continually monitor the bias voltages (PVCC and VCC) and
the voltage at the EN pin. The POR function initiates
soft-start operation 384 clock cycles after the EN pin voltage
is pulled to be above 0.8V, all input supplies exceed their
POR thresholds and the PLL locking time expires, as shown
in Figure 4. The enable pin can be used as a voltage monitor
and to set desired hysteresis with an internal 30
current going through an external resistor divider. The
sinking current is disengaged after the system is enabled.
This feature is especially designed for applications that
require higher input rail POR for better undervoltage
protection. For example, in 12V applications, R
and R
(V
with 1.6V hysteresis (V
During shutdown or fault conditions, the soft-start is reset
quickly while UGATE and LGATE change states immediately
(<100ns) upon the input drop below falling POR.
Δ
R UP
V
V
EN_RTH
PLL LOCKING
EN_FTH
FIGURE 4. SOFT-START INITIALIZATION LOGIC
EN1/FF1 POR
EN2/FF2 POR
RAMP
PVCC POR
PVCC POR
=
DOWN
VCC POR
VCC POR
V
---------------------------- -
I
EN_HYS
EN_HYS
=
) to 10.6V and turn-off threshold (V
=
LIMIT(V
V
HIGH = ABOVE POR; LOW = BELOW POR
= 5.23k will set the turn-on threshold
EN_RTH
CC_FF
–
V
EN_HYS
EN_HYS
R DOWN
AND
SYSTEM DELAY
×
AND
G
RAMP
23
FIGURE 5. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT
).
=
, VCC - 1.4V - V
-------------------------------------------------------------- -
V
EN_FTH
R
Cycles
UP
Cycles
384
384
•
V
–
EN_REF
V
EN_FTH
SOFT-START
OF CHANNEL 1
EN_REF
RAMP_OFFSET
SOFT-START
OF CHANNEL 2
R
UP
R
DOWN
µ
A sinking
UP
= 53.6k
VIN
) to 9V,
ISL8120
)
VCC
EN/FF
0.8V
Voltage Feed-forward
Other than used as a voltage monitor described in the
previous section, the voltages applied to the EN/FF pins are
also fed to adjust the amplitude of each channel’s individual
sawtooth. The amplitude of each channel’s sawtooth is set to
1.25 times the corresponding EN/FF voltage upon its enable
(above 0.8V). This helps to maintain a constant gain
(
and the input voltage to achieve optimum loop response
over a wide input voltage range. The sawtooth ramp offset
voltage is 1V (equal to 0.8V*1.25), and the peak of the
sawtooth is limited to VCC - 1.4V. With VCC = 5.4V, the
ramp has a maximum peak-to-peak amplitude of VCC - 2.4V
(equal to 3V); so the feed-forward voltage effective range is
typically 3x as the ramp amplitude ranges from 1V to 3V.
A 384 cycle delay is added after the system reaches its
rising POR and prior to the soft-start. The RC timing at the
EN/FF pin should be sufficiently small to ensure that the
input bus reaches its static state and the internal ramp
circuitry stabilizes before soft-start. A large RC could cause
the internal ramp amplitude not to synchronize with the input
bus voltage during output start-up or when recovering from
faults. It is recommended to use open drain or open collector
to gate this pin for any system delay, as shown in Figure 5.
The multiphase system can immediately turn off all ICs
under fault conditions of one or more phases by pulling all
EN/FF pins low. Thus, no bouncing occurs among channels
at fault and no single phase could carry all current and be
over stressed.
G
M
OV, OT, OC, AND PLL LOCKING FAULTS (ONLY FOR EN/FF1)
V
G
CC_FF
=
0.8V
RAMP
I
VIN D
EN_HYS
= 1.25
⋅
V
MAX
= 30µA
RAMP_OFFSET
∑
⁄
ΔV
RAMP
VCC - 1.4V
LIMITER
= 1.0V
384 Clock
Cycles
) contributed by the modulator
SAWTOOTH
AMPLITUDE
(ΔV
RAMP
SOFT-START
)
UPPER LIMIT
LOWER LIMIT
(RAMP OFFSET)
March 20, 2009
FN6641.0