isl8120 Intersil Corporation, isl8120 Datasheet
isl8120
Available stocks
Related parts for isl8120
isl8120 Summary of contents
Page 1
... DDR tracking applications (VDDQ and VTT outputs). The output voltage of a ISL8120-based converter can be precisely regulated to as low as the internal reference voltage 0.6V, with a system accuracy of ±0.6% over commercial temperature and line load variations. Channel 2 can track an external ramp signal for DDR/tracking applications ...
Page 2
... ISL8120IRZ ISL8120 IRZ - QFN ISL8120IRZ-T* ISL8120 IRZ - QFN * Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
Page 3
Block Diagram (1/2) REFERENCE V = 0.6V REF VCC 700mV FB1 COMP1 VSEN1+ VSEN1- UNITY GAIN DIFF AMP1 VMON1 EN/FF1 VCC PVCC POWER-ON RESET (POR) OTP OVER-TEMPERATURE PROTECTION (OTP) CHANNEL 1 SOFT-START AND FAULT LOGIC V SAW1 REF AVG_OCP + ...
Page 4
Block Diagram (2/2) RELATIVE PHASE CONTROL k*VDDQ V REF VCC 700mV FB2 COMP2 V REF VSEN2+ VSEN2- UNITY GAIN DIFF AMP2 VMON2 CLKOUT/REFIN EN/FF2 OTP POR MASTER CLOCK OSCILLATOR GENERATOR CHANNEL 2 SOFT-START AND FAULT LOGIC V REF2 SAW2 M/D ...
Page 5
... Typical Application I (Dual Regulators with DCR Sensing and Remote Sense) VIN +3.3 TO +22V C F2 VIN C F3 ISL8120 CLKOUT/REFIN VCC PGOOD R FS FSYNC EN2/FF2 EN1/FF1 R SET ISET ISHARE 5 ISL8120 VIN_F HFIN C F1 VCC PVCC BOOT1 UGATE1 Q1 PHASE1 LGATE1 Ω ISEN1A ISEN1B ...
Page 6
... Note 1: Set the upper resistor little higher than R*(VDDQ/0 will set the final REFIN voltage (stead state voltage after soft-start) derived from the VDDQ little higher than internal 0.6V reference. In this way, the VTT final voltage will use the internal 0.6V reference after soft-start. Note 2: Another way to set REFIN voltage is to connect VMON1 directly to REFIN pin. 6 ISL8120 VIN_F L IN ...
Page 7
... CLKOUT/REFIN FB2 GND VSEN2+ 7 ISL8120 DS(ON VCC PVCC BOOT1 UGATE1 PHASE1 LGATE1 ISEN1A R ISEN1B COMP1/2 ISL8120 Z COMP1 FB1 VMON1/2 VSEN1+ VSEN1- VIN_F BOOT2 UGATE2 PHASE2 LGATE2 ISEN2A R ISEN2 ISEN2B VCC VSEN2- GND Sensing and Voltage Trimming) C HFIN C BIN C ...
Page 8
... FB2 ISHARE VMON2 VSEN2+ ISET VSEN2- R PVCC VCC BOOT1 VIN UGATE1 FSYNC PHASE1 R FS EN/FF1,2 LGATE1 PGOOD ISL8120 EN/FF1,2 ISEN1A PHASE 1 AND 3 BOOT2 ISEN1B UGATE2 COMP1/2 PHASE2 FB1 VMON1/2 LGATE2 VSEN1+ ISEN2A VSEN1- ISEN2B ISHARE FB2 VSEN2+ VSEN2- CLKOUT/REFIN ISET ...
Page 9
... ISEN1A PHASE 2 AND 4 ISEN1B FB2 COMP1/2 FB1 VMON1/2 ISET R GND FSYNC ISHARE R PVCC VCC CC BOOT1 VIN UGATE1 FSYNC PHASE1 R FS LGATE1 ISL8120 ISEN1A ISEN1B PHASE 1 AND 3 COMP1/2 FB1 VMON1/2 VSEN1+ VSEN1- ISHARE FB2 CLKOUT/REFIN GND ISET R VIN_F BOOT2 Q1 L OUT2 ...
Page 10
... ISHARE VMON2 VSEN2+ GND PHASE 2 VSEN2- R PVCC VCC BOOT1 VIN UGATE1 FSYNC PHASE1 R FS LGATE1 PGOOD EN/FF1,2 ISEN1A ISL8120 BOOT2 ISEN1B UGATE2 Q3 COMP1/2 PHASE2 FB1 VMON1/2 LGATE2 Q4 VSEN1+ ISEN2A VSEN1- ISEN2B ISHARE FB2 PHASE 1 AND 3 VSEN2+ CLKOUT/REFIN GND VSEN2- VCC ...
Page 11
... CLKOUT/REFIN FSYNC ISHARE FB2 PHASE 2 AND 5 ISET GND R R VCC PVCC BOOT1 VIN UGATE1 PHASE1 LGATE1 ISEN1A ISEN1B VMON1 FB1 COMP1/2 ISL8120 VMON2 R OS1 VSEN1+ VSEN1- ISHARE FB2 CLKOUT/REFIN PHASE 1 AND 4 ISET GND R VIN_F BOOT3 Q1 L OUT3 Q2 R ISEN3 ...
Page 12
... FSYNC MODULE #1 FB2 ISHARE GND ISET R R PVCC VCC CC1 BOOT1 VIN UGATE1 FSYNC PHASE1 R FS LGATE1 ISEN1A ISEN1B COMP1/2 FB1 ISL8120 VMON1/2 VSEN1+ VSEN1- ISHARE 2-PHASE MODULE #2 FB2 CLKOUT/REFIN GND ISET R VIN_F BOOT3 Q5 L OUT3 C Q6 OUT2 ...
Page 13
... VSEN1+ VSEN1- CLKOUT/REFIN FSYNC ISHARE/ISET FB2 GND OUTPUT 2 R VCC PVCC BOOT1 VIN UGATE1 PHASE1 LGATE1 ISEN1A ISEN1B VMON1 FB1 ISL8120 COMP1/2 (PHASE 1 and 4) VMON2 R OS1 VSEN1+ VSEN1- ISHARE/ISET FB2 CLKOUT/REFIN OUTPUT 1 GND VIN_F BOOT3 Q1 L OUT3 V OUT3 Q2 ...
Page 14
... EN = 0V, PVCC = 5V PVCC 0V, VCC = 3V VCC I PVCC = 4V TO 5.6V PVCC PVCC = P-Channel MOSFET (VIN = 5V) LDO PVCC I = 0mA to 250mA PVCC ISL8120CRZ ISL8120IRZ t After PLL, VCC, and PVCC PORs, and SS_DLY EN(s) above their thresholds I EN_HYS V = 10.6V; V EN_RTH EN_FTH V EN_HYS R = 53.6kΩ 5.23kΩ UP DOWN θ ...
Page 15
... V = 0V; VCC<3.4V RAMP EN V RAMP_OS VCC = 5.4V (2.97V) VCC = 5.4V (2.97V MIN_OFF t BLANKING V ISL8120CRZ REF1 ISL8120IRZ V ISL8120CRZ REF2 ISL8120IRZ R = 10k 100p, at COMP Pin 10k 100p, at COMP Pin UGBW_EA L L VCC= 10k 100p, at COMP Pin SR_EA Positive Direction Into the FB pin ...
Page 16
... R 45mA Source Current LGATE R 45mA Sink Current LGATE I VCC = 2.97V to 5.6V SOURCE I VCC = 5V; ISL8120CRZ SOURCE VCC = 5V; ISL8120IRZ VCC = 2.97V to 5.6V V OC_SET (comparator offset included) V VCC = 2.97V to 5.6V OC_SET_HYS (comparator offset included) VCC = 2.97V and 3.6V, 1% Resistor Sense, 10mV Signal VCC = 4.5V and 5.6V, 1% Resistor Sense, 10mV Signal VCC = 2 ...
Page 17
... ISL8120 connected to a switching square pulse waveform, typically the CLKOUT input signal from another ISL8120 or an external clock. The internal oscillator synchronizes with the leading edge of the input signal. EN/FF1, 2 (Pins 4, 6) These are triple function pins ...
Page 18
... Channel 2’s internal reference through this pin for DDR/tracking applications (see “Internal Reference and System Accuracy” on page 32). 2) The ISL8120 operates as a dual-PWM controller for two independent regulators with selectable phase degree shift, which is programmed by the voltage level on REFIN (see “ ...
Page 19
... Channel 1’s clock signal (falling edge of PWM) to synchronize with another ISL8120, which can operate at Mode 3, 4, 5A, or 7A. A 4-phase single output converter can be constructed with two ISL8120s operating in Mode (Mode 7A). If the share bus is not connected between ICs, each IC could generate an independent output (Mode 7B) ...
Page 20
... VCC VCC VCC VCC VCC VCC VCC VCC 8 Cascaded IC Operation MODEs 5A+5A+7A+5A+5A+5A/7A, No External Clock Required 9 External Clock or External Logic Circuits Required for Equal Phase Interval 20 ISL8120 TABLE 1. ISHARE (I/O) REPRESENTS CLKOUT/REFIN WHICH VSEN2 WRT 1ST CHANNEL( CURRENT - - - - N CHANNEL ST 1 CHANNEL ...
Page 21
... CLKOUT (1 IC) 120° ND CH1 UG (2 IC) ND CH2 UG(2 IC, OFF, EN2/FF2 = 0) VCC VSEN2- VSEN2+ 700mV DIFF AMP2 FIGURE 3. SIMPLIFIED RELATIVE PHASES CONTROL 21 ISL8120 1-D 180° D 90° D 180° PHASE TIMING DIAGRAM (MODE 7A) 1-D 240° D 120° 1 -PHASE TIMING DIAGRAM (MODE 6) ...
Page 22
... Functional Description Initialization Initially, the ISL8120 Power-On Reset (POR) circuits continually monitor the bias voltages (PVCC and VCC) and the voltage at EN pin. The POR function initiates soft-start operation 384 clock cycles after the EN pin voltage is pulled to be above 0.8V, all input supplies exceed their POR thresholds and the PLL locking time expires, as shown in Figure 4 ...
Page 23
... The ISL8120 has the ability to work under a pre-charged output (see Figure 8). The output voltage would not be yanked down during pre-charged start-up. If the pre-charged output voltage is greater than the final target level but prior to 113% setpoint, the switching will not start until the output voltage reduces to the target voltage and the first PWM pulse is generated (see Figure 9) ...
Page 24
... OV event with the corresponding VMON as the monitor. In multiphase mode, both channels respond simultaneously when either triggers an OV event. 24 ISL8120 To protect the overall power trains in case of only one channel of a multiphase system detecting OV, the low-side MOSFET always turns on at the conditions of EN/FF = LOW ...
Page 25
... Current Loop When the ISL8120 operates in 2-phase mode, the current control loop keeps the channel’s current in balance. After 175ns blanking period with respect to the falling edge of the PWM pulse of each channel, the voltage developed across the DCR of the inductor the low-side MOSFETs, DS(ON precision resistor, is filtered and sampled for 175ns ...
Page 26
... If one single external resistor is used as R ISHARE bus to ground for all the ICs in parallel, R should be set equal to R number of the ISL8120 controllers in parallel or multiphase operations), and the share bus voltage (V R ISHARE . The CS1 channels ...
Page 27
... VSEN- pulled to VCC, as shown in Figure 15. Current Share Control Loop in Multi-Module with Independent Voltage Loop The power module controlled by ISL8120 with its own voltage loop can be paralleled to supply one common output load with its integrated Master-Slave current sharing control, as shown in “Typical Application VIII (Multiple Power Modules in Parallel with Current Sharing Control)” ...
Page 28
... When VIN drops below 5.0V, the pass element will saturate; PVCC will track VIN, minus the dropout of the linear 28 ISL8120 regulator. When used with an external 5V supply, VIN pin is recommended to be tied directly to PVCC. 2.65V TO 5.6V 2Ω ...
Page 29
... connecting the FSYNC pin to an external square pulse GD waveform (such as the CLOCK signal, typically 50% duty cycle from another ISL8120), the ISL8120 will synchronize C DS its switching frequency to the fundamental frequency of the GI1 input waveform. The maximum voltage to FSYNC pin is ...
Page 30
... As some applications will not need the differential remote sense, the output of the remote sense buffer can be disabled and be placed in high impedance by pulling VSEN- within 700mV of VCC. In such an event, the VMON pin can be 30 ISL8120 VOUT ...
Page 31
... In DDR mode, Channel 1 delays 60° over Channel 2. In Dual mode, depending upon the resistor divider level of REFIN from VCC, the ISL8120 operates as a dual-PWM controller for two independent regulators with a phase shift as shown in Table 2. The phase shift is latched as VCC raises above POR and cannot be changed on the fly ...
Page 32
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 32 ISL8120 %max R ) should be OS_DA 2 ...
Page 33
... Package Outline Drawing L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 11/07 5.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 4. 80 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 33 ISL8120 ± 0.1 ( 28X (32X 32X 0 . 60) NOTES: 1. Dimensions are in millimeters. Dimensions ...