FM75M8 Fairchild Semiconductor, FM75M8 Datasheet - Page 13

• Manufacturer Part Number: FM75M8
• Description: TEMPERATURE SENSOR LV 8SOIC
• Manufacturer: Fairchild Semiconductor

Specifications of FM75M8

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Comparator, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -40°C ~ 125°C
• Output Type: SMBus™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Full Temp Accuracy: 4 C
• Digital Output - Bus Interface: I2C, SMBus
• Digital Output - Number Of Bits: 9 bit to 12 bit
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Description/function: Semiconductor
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Current: 500 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

© 2006 Fairchild Semiconductor Corporation
FM75 Rev. 1.0.8
Timing Diagrams
SCL
SDA
SDA
SCL
. . .
SDA
. . .
SCL
Repeat
Master
Start
from
S
SDA
SCL
Figure 12. Two-byte Read from Preset Pointer Location (Temperature, T
S
S
1
1
1
0
0
Figure 11. Pointer Set Followed by Immediate Read from a Two-byte Register
0
S
0
Figure 13. One-byte Read from Configuration Register with Preset Pointer
0
Address Byte
0
1
Address Byte
Address
1
1
Byte
1
0
A2
A2
A2
A1
A1
0
Address Byte
A1
A0
A0
1
A0
R/W
R/W
(Temperature, T
A2
R/W
FM75
FM75
from
from
Ack
Ack
A
A
FM75
from
Ack
A1
A
D7
D7
A0
0
D6
D6
Most Significant Data
Most Significant Data
R/W
0
D5
D5
(from FM75)
(from FM75)
0
OS
Pointer Byte
D4
FM75
D4 D3
from
Byte
Byte
Ack
A
13
Note: This segment of this timing diagram is a generic
pointer set cycle that must be followed by either an
immediate read cycle or write cycle, as shown in this
figure and in figures 10, 11, and 12.
, or T
0
D3
X
0
D2
D2
HYST
D6
0
D1
D1 D0
Register)
D5
P1
D0
(from FM75)
Data Byte
Master
Master
from
from
Ack
Ack
P0
D4
A
A
aTS75
from
Ack
D7
D7
A
D3
Least Significant Data Byte
D6
D6 D5
Least Significant Data
. . . .
. . . .
D2
OS
D5
(from FM75)
(from FM75)
, or T
D1
D4
D4
Byte
D0
0
HYST
0
No Ack
Master
0
from
N
0
Register)
0
0
P
0
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0
No Ack
Master
No Ack
Master
from
from
N
N
P
P