ADT7473ARQZ-1R7 ON Semiconductor, ADT7473ARQZ-1R7 Datasheet - Page 20

• Manufacturer Part Number: ADT7473ARQZ-1R7
• Description: IC THERM MON FAN CTLR 16-QSOP
• Manufacturer: ON Semiconductor
• Series: dBCool®r

Specifications of ADT7473ARQZ-1R7

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Fan Speed Counter, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Full Temp Accuracy: +/- 0.5 C
• Digital Output - Bus Interface: Serial (3-Wire, 4-Wire)
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

monitoring cycle time for voltage and temperature
monitoring with averaging disabled is 19 ms. The ADT7473/
ADT7473−1 is a derivative of the ADT7467. As a result, the
total conversion time in the ADT7473/ ADT7473−1 is the
same as the total conversion time of the ADT7467, even
though the ADT7473/ADT7473−1 has fewer monitored
channels.
synchronized with the analog measurements in any way.
Interrupt Status Registers
Status Register 1 and Interrupt Status Register 2. The status
register bit for each channel reflects the status of the last
measurement and limit comparison on that channel. If a
measurement is within limits, the corresponding status
register bit is cleared to 0. If the measurement is out of limits,
the corresponding status register bit is set to 1.
polled by reading the status registers over the serial bus. In
Bit 7 (OOL) of Interrupt Status Register 1 (Reg. 0x41), a 1
means an out−of−limit event has been flagged in Interrupt
Status Register 2. This means the user needs only to read
Interrupt Status Register 2 when this bit is set. Alternatively,
Pin 5 or Pin 9 on the ADT7473 can be configured as an
SMBALERT output, while only Pin 9 can be configured to
be an SMBALERT on the ADT7473−1. This automatically
notifies the system supervisor of an out−of−limit condition.
Reading the status registers clears the appropriate status bit
as long as the error condition that caused the interrupt has
cleared. Status register bits (except OVT) are sticky.
Whenever a status bit is set, indicating an out−of−limit
condition, it remains set even if the event that caused it has
gone away (until read). The only way to clear the status bit
is to read the status register after the event has gone away.
Interrupt mask registers (Register 0x74 and Register 0x75)
allow individual interrupt sources to be masked from
causing an SMBALERT. However, if one of these masked
interrupt sources goes out of limit, its associated status bit is
set in the interrupt status registers. OVT clears
automatically.
Interrupt Status Register 1 (0x41)
Bit 7 (OOL) = 1, denotes a bit in Interrupt Status Register 2
is set and Interrupt Status Register 2 should be read.
Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has
been exceeded.
Bit 5 (LT) = 1, local temperature high or low limit has been
exceeded.
Bit 4 (R1T) = 1, Remote 1 temperature high or low limit has
been exceeded.
Bit 2 (V
Bit 1 (V
Interrupt Status Register 2 (0x42)
Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.
Fan TACH measurements are made in parallel and are not
The results of limit comparisons are stored in Interrupt
The state of the various measurement channels can be
CCP
CC
) = 1, V
) = 1, V
CC
CCP
high or low limit has been exceeded.
high or low limit has been exceeded.
http://onsemi.com
20
Bit 6 (D1) = 1, indicates an open or short on D1+/D1– inputs.
Bit 5 (F4P) = 1, indicates Fan 4 has dropped below the
minimum speed. Alternatively, it indicates the THERM
limit has been exceeded, if the THERM function is used.
Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below the
minimum speed.
Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below the
minimum speed.
Bit 2 (FAN1) = 1, indicates that Fan 1 dropped below the
minimum speed.
Bit 1 (OVT) = 1, indicates that a THERM overtemperature
limit has been exceeded.
Bit 0 (THERM Limit Latch) = 1, indicates a Remote
Channel 2 latch.
SMBALERT Interrupt Behavior
SMBALERT interrupt can be generated for out−of−limit
conditions. It is important to note how the SMBALERT
output and status bits behave when writing interrupt handler
software.
status bits behave. Once a limit is exceeded, the
corresponding status bit is set to 1. The interrupt status bit
remains set until the error condition subsides and the
interrupt status register is read. The status bits are referred
to as sticky because they remain set until read by software.
This ensures that an out−of−limit event cannot be missed if
software is polling the device periodically. Note that the
SMBALERT output remains low for the entire duration that
a reading is out of limit and until the interrupt status register
has been read. This has implications on how software
handles the interrupt.
resetting immediately after the overtemperature condition
ceases. This also applies to SMBALERT if associated with
an OVT event.
Handling SMBALERT Interrupts
interrupts, it is recommended to handle the SMBALERT
interrupt as follows:
HIGH LIMIT
TEMPERATURE
STATUS BIT
SMBALERT
The ADT747/ADT7473−1 can be polled for status, or an
Figure 29 shows how the SMBALERT output and sticky
Note that THERM overtemperature events are not sticky,
To prevent the system from being tied up servicing
STICKY
Figure 29. SMBALERT and Status Bit Behavior
1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
(TEMP BELOW LIMIT)
CLEARED ON READ