PCA9530DP,118 NXP Semiconductors, PCA9530DP,118 Datasheet - Page 8

• Manufacturer Part Number: PCA9530DP,118
• Description: IC LED DRIVER RGB 8-TSSOP
• Manufacturer: NXP Semiconductors
• Type: RGB LED Driverr

Specifications of PCA9530DP,118

• Package / Case: 8-TSSOP
• Topology: Open Drain, PWM
• Number Of Outputs: 2
• Internal Driver: Yes
• Type - Primary: Backlight, LED Blinker
• Type - Secondary: RGB
• Frequency: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 25mA
• Internal Switch(s): Yes
• Low Level Output Current: 6.5 mA
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Supply Current: 500 uA
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Efficiency: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1831-2; 935276297118; PCA9530DP-T

NXP Semiconductors
PCA9530_3
Product data sheet
Fig 8.
SDA
SCL
System configuration
TRANSMITTER/
RECEIVER
MASTER
7.2 System configuration
7.3 Acknowledge
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 9.
RECEIVER
Acknowledgement on the I
SLAVE
SCL from master
by transmitter
data output
by receiver
data output
Rev. 03 — 26 February 2009
TRANSMITTER/
RECEIVER
condition
START
SLAVE
S
Figure
2
C-bus
TRANSMITTER
1
8).
MASTER
2
TRANSMITTER/
RECEIVER
MASTER
acknowledgement
not acknowledge
SLAVE
clock pulse for
acknowledge
8
2-bit I
2
MULTIPLEXER
C-bus LED dimmer
PCA9530
© NXP B.V. 2009. All rights reserved.
002aaa987
I
2
9
C-BUS
002aaa966
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