DS1862AB+ Maxim Integrated Products, DS1862AB+ Datasheet - Page 26

• Manufacturer Part Number: DS1862AB+
• Description: IC LASR CTRLR 7CHAN 5.5V 25CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Laser Diode Controller (Fiber Optic)r

Specifications of DS1862AB+

• Data Rate: 10Gbps
• Number Of Channels: 7
• Voltage - Supply: 2.9 V ~ 5.5 V
• Current - Supply: 3mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 25-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XFP Laser Control and Digital Diagnostic IC
ADDRESS
* Bit 0 of Address 01h can be written only if bit 0 of Byte DDh in Table 01h is set.
** V
26
00
38
70
78
BYTE
(hex)
08
10
18
20
28
30
40
48
50
58
60
68
(hex)
01
50
51
52
53
54
55
56
CC2/3
<0,2>
<0,2>
<0,1>
<0,1>
<2>
<2>
<2>
<2>
<2>
<2>
<1>
<1>
<1>
<1>
<1>
<1>
______________________________________________________________________________________
are in reserved locations.
Temp/Res/Bias/
Temp/Res/Bias/
Signal Cond
USER SRAM
BYTE/WORD
TxP Alarm
Reserved
TxP Mask
BYTE 0/8
Reserved
USER EE
Host PW
NAME
<1>
<1>
<1>
<1>
<1>
<1>
<1>
V
Temp Warn Lo
AUX1 Warn Lo
AUX2 Warn Lo
Bias Warn Lo
RX-P Warn Lo
TX-P Warn Lo
CC3
Temp Value
RX-P Value
WORD 0
<1>
Warn Lo**
*
RxP/AUX1/AUX2/
RxP/AUX1/AUX2/
Signal Cond*
USER SRAM
L-HI-RX-P-W
L-APD-SUP-F
Res Alarm
BYTE 1/9
Reserved
Res Mask
Reserved
bit
L-HI-TEMP-
L-HI-TEMP-
Host PW
L-HI-RX-P-
L-HI-V
USER EE
L-TX-NR
15
Bit7
AL
AL
AL
W
CC5
bit
14
-
L-LO-TEMP-
L-LO-TEMP-
bit
L-LO–V
L-LO-RX-P-
L-LO-RX-P-
Temp/Res/Bias/
Temp/Res/Bias/
USER EE
L-TEC-F
USER SRAM
13
L-TX-F
Bit6*
TxP Mask
Reserved
TxP Warn
BYTE 2/A
USER EE
Reserved
AL
AL
AL
W
W
Host PW
bit
CC5-
V
Temp Alarm Hi
AUX1 Alarm Hi
AUX2 Alarm Hi
12
V
LOWER MEMORY (00h–7Fh)
Bias Alarm Hi
TX-P Alarm Hi
RX-P Alarm Hi
CC3
CC2/3
AUX1 Value
WORD 1
bit
L-WAVE-NL
L-HI-AUX1-
L-HI-AUX1-
Alarm Hi**
EXPANDED BYTES
L-TX-CDR-
L-HI-V
Reserved
Reserved
USER EE
11
Value**
Bit5
AUX2/Res Mask
AUX2/Res Warn
NL
AL
AL
W
USER SRAM
RxP/AUX1/
RxP/AUX1/
CC3
bit
Reserved
BYTE 3/B
USER EE
Reserved
10
-
L-LO-AUX1-
L-LO-AUX1-
L-LO–V
PWE (MSB)
bit
Reserved
Reserved
Reserved
USER EE
L-RX-NR
9
Bit4
AL
AL
W
USER SRAM
CC3
bit
Rx/Rx Misc
Tx/Rx Misc
BYTE 4/C
Reserved
Reserved
8
Flags
Mask
-
POA
L-HI-BIAS-W L-LO-BIAS-W L-HI-TX-P-W L-LO-TX-P-W
V
Temp Alarm Lo
AUX1 Alarm Lo
AUX2 Alarm Lo
L-HI-AUX2-
L-HI-AUX2-
bit
L-HI-BIAS-
Bias Alarm Lo
RX-P Alarm Lo
L-HI-V
TX-P Alarm Lo
Reserved
CC3
L-RX-LOS
USER EE
AUX2 Value
Bias Value
7
WORD 2
Bit3
AL
AL
AL
W
Alarm Lo**
CC2
Wave/Res Flags
Apd/Tec/Wave/
bit
USER SRAM
Res Mask
6
BYTE 5/D
-
Reserved
Reserved
Reserved
Apd/Tec/
L-LO-AUX2-
L-LO-AUX2-
L-LO–V
L-LO-BIAS-
L-RX-CDR-
bit
EN2 Value
Reserved
5
Bit2
PWE (LSB)
NL
AL
AL
AL
W
CC2-
bit
4
USER SRAM
USER SRAM
V
Alarm Flags
V
Alarm Mask
BYTE 6/E
Reserved
CC5/3/2
CC5/3/2/
PEC_EN
bit
L-MOD-NR
GCS1
EN1 Value
L-HI-V
L-HI-TX-P-
Reserved
Reserved
Reserved
3
V
Bit1
Temp Warn Hi
AUX1 Warn Hi
AUX2 Warn Hi
AL
AL
Bias Warn Hi
RX-P Warn Hi
CC3
TX-P Warn Hi
/Vee
Vee
TX-P Value
WORD 3
EE5
bit
Warn Hi**
2
-
USER SRAM
USER SRAM
Table Select
V
V
Warn Flags
Warn Mask
Lock-T1-221
BYTE 7/F
Reserved
CC5/3/2
CC5/3/2
L-LO-V
bit
Host PW
Reserved
Reserved
Reserved
L-RESET-
L-LO-TX-
GCS0
DONE
1
P-AL
Bit0
AL
/Vee
/Vee
EE5
bit
0
-