ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 91

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 51. CONSEL[1:0] Bits in Energy Registers
Energy Registers
AWATTHR, AFWATTHR
BWATTHR, BFWATTHR
CWATTHR, CFWATTHR
AVARHR, AFVARHR
BVARHR, BFVARHR
CVARHR, CFVARHR
AVAHR
BVAHR
CVAHR
Table 52. LCYCMODE Register (Address 0xE702)
Bit
Location
0
1
2
3
4
5
6
7
Table 53. HSDC_CFG Register (Address 0xE706)
Bit
Location
0
1
2
LWATT
LVAR
LVA
ZXSEL[0]
ZXSEL[1]
ZXSEL[2]
RSTREAD
Reserved
Bit Mnemonic
HCLK
HSIZE
HGAP
Bit Mnemonic
Default Value
0
0
0
1
1
1
1
0
Default Value
0
0
0
CONSEL[1:0] = 00
VA × IA
VB × IB
VC × IC
VA × IA’
VB × IB’
VC × IC’
VA rms × IA rms
VB rms × IB rms
VC rms × IC rms
0: Phase A is not selected for zero-crossings counts in the line cycle accumulation mode.
Description
0: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) are placed in regular accumulation mode.
1: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR,
BFWATTHR, and CFWATTHR) are placed into line cycle accumulation mode.
0: the var-hour accumulation registers (AVARHR, BVARHR, and CVARHR) are placed in regular
accumulation mode. This bit is always 0 for the ADE7854.
1: the var-hour accumulation registers (AVARHR, BVARHR, and CVARHR) are placed into line-
cycle accumulation mode.
0: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed in regular
accumulation mode.
1: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are placed into line-cycle
accumulation mode.
1: Phase A is selected for zero-crossings counts in the line cycle accumulation mode. If more
than one phase is selected for zero-crossing detection, the accumulation time is shortened
accordingly.
0: Phase B is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase B is selected for zero-crossings counts in the line cycle accumulation mode.
0: Phase C is not selected for zero-crossings counts in the line cycle accumulation mode.
1: Phase C is selected for zero-crossings counts in the line cycle accumulation mode.
0: read-with-reset of all energy registers is disabled. Clear this bit to 0 when Bits[2:0] (LWATT,
LVAR, and LVA) are set to 1.
1: enables read-with-reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR
registers. This means a read of those registers resets them to 0.
Reserved. This bit does not manage any functionality.
Description
0: HSCLK is 8 MHz.
1: HSCLK is 4 MHz.
0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first.
1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.
0: no gap is introduced between packages.
1: a gap of seven HCLK cycles is introduced between packages.
CONSEL[1:0] = 01
VA × IA
0
VC × IC
VA × IA’
0
VC × IC’
VA rms × IA rms
0
VC rms × IC rms
Rev. D| Page 91 of 96
ADE7854/ADE7858/ADE7868/ADE7878
CONSEL[1:0] = 10
VA × IA
VB = −VA − VC
VB × IB
VC × IC
VA × IA’
VB = −VA − VC
VB × IB’
VC × IC’
VA rms × IA rms
VB rms × IB rms
VC rms × IC rms
CONSEL[1:0] = 11
VA × IA
VB = −VA
VB × IB
VC × IC
VA × IA’
VB = −VA
VB × IB’
VC × IC’
VA rms × IA rms
VB rms × IB rms
VC rms × IC rms