ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet
ADE7878ACPZ
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ADE7878ACPZ Summary of contents
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FEATURES Highly accurate; supports EN 50470-1, EN 50470-3, IEC 62053-21, IEC 62053-22, and IEC 62053-23 standards Compatible with 3-phase 4-wire (delta or wye), and other 3-phase services Supplies total (fundamental and harmonic) active/reactive/ apparent energy and fundamental active/reactive ...
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ADE7878 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 Timing Characteristics ................................................................ 8 Absolute Maximum Ratings .......................................................... 11 Thermal Resistance .................................................................... 11 ESD ...
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Apparent Power Calculation Using VNOM ........................ 53 Apparent Energy Calculation ................................................ 53 Integration Time Under Steady Load ................................... 54 Energy Accumulation Mode .................................................. 54 Line Cycle Apparent Energy Accumulation Mode ............. 54 Waveform Sampling Mode ........................................................ 55 Energy-to-Frequency Conversion ............................................ ...
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ADE7878 FUNCTIONAL BLOCK DIAGRAM Figure 1. Rev Page 08510-201 ...
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SPECIFICATIONS VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, T Table Parameter ACCURACY Active Energy Measurement Active Energy Measurement Error (per Phase) Total Active Power Fundamental Active ...
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ADE7878 1, 2 Parameter DC Power Supply Rejection Output Frequency Variation Total Reactive Energy Measurement Bandwidth RMS MEASUREMENTS I rms and V rms Measurement Bandwidth I rms and V rms Measurement Error (PSM0 Mode) MEAN ABSOLUTE VALUE (MAV) MEASUREMENT Imav ...
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Parameter CLKIN Input Clock Frequency Crystal Equivalent Series Resistance CLKIN Input Capacitance CLKOUT Output Capacitance LOGIC INPUTS—MOSI/SDA, SCLK/SCL, CLKIN RESET , PM0, AND PM1 Input High Voltage, V INH Input Low Voltage, V INL Input Current, ...
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ADE7878 TIMING CHARACTERISTICS VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz Table 2. I C-Compatible Interface Timing Parameter Parameter SCL Clock Frequency Hold Time (Repeated) Start Condition Low ...
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Table 3. SPI Interface Timing Parameters Parameter SS to SCLK Edge SCLK Period SCLK Low Pulse Width SCLK High Pulse Width Data Output Valid After SCLK Edge Data Input Setup Time Before SCLK Edge Data Input Hold Time After SCLK ...
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ADE7878 Table 4. HSDC Interface Timing Parameter Parameter HSA to SCLK Edge HSCLK Period HSCLK Low Pulse Width HSCLK High Pulse Width Data Output Valid After HSCLK Edge Data Output Fall Time Data Output Rise Time HSCLK Rise Time HSCLK ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 5. Absolute Maximum Ratings Parameter VDD to AGND VDD to DGND Analog Input Voltage to AGND, IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP, VCP, VN Analog Input Voltage ...
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ADE7878 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 7. Pin Function Descriptions Pin No. Mnemonic 1, 10, 11, 20, NC 21, 30, 31 PM0 3 PM1 4 RESET 5 DVDD 6 DGND 7, 8 IAP, IAN 9, 12 IBP, ...
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Pin No. Mnemonic 18, 19, 22, 23 VN, VCP, VBP, VAP 24 AVDD 25 AGND 26 VDD 27 CLKIN 28 CLKOUT 29, 32 IRQ0 , IRQ1 33, 34, 35 CF1, CF2, CF3/HSCLK 36 SCLK/SCL 37 MISO/HSD 38 MOSI/SDA 39 SS ...
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ADE7878 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 –0.35 –0.40 0.01 0.1 1 FULL-SCALE CURRENT (%) Figure 7. Total Active Energy Error As Percentage of Reading (Gain = + over Temperature with ...
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V = 2.97V DD 0. 3.30V 3.63V DD 0.10 0 –0.10 –0.20 –0.30 0.01 0.1 1 FULL-SCALE CURRENT (%) Figure 13. Total Reactive Energy Error As Percentage of Reading (Gain = +1) over Power ...
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ADE7878 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 0.01 0.10 1.00 FULL-SCALE CURRENT (%) Figure 19. CF Fundamental Reactive Energy Error As a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off 0.50 0.40 0.30 0.20 0.10 ...
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TEST CIRCUIT 10kΩ 1kΩ 1.8nF 1.8nF 1kΩ 1kΩ 1.8nF 1.8nF 1kΩ 3. 0.22µF 4.7µF 10µ 3.3V PM0 2 SS/HSA 39 PM1 3 1µF MOSI/SDA 38 RESET 4 MISO/HSD 37 IAP 7 SCLK/SCL 36 IAN 8 ...
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ADE7878 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7878 is defined by Measurement Error = − Energy Registered by ADE 7878 True True Energy Phase Error Between Channels The high-pass filter (HPF) and digital ...
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POWER MANAGEMENT The ADE7878 has four modes of operation, determined by the state of the PM0 and PM1 pins (see Table 8). These pins provide complete control of the ADE7878 operation and can easily be connected to an external microprocessor ...
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ADE7878 IRQ pin is triggered low at the end of a measurement period, 0 this signifies all phase currents stayed below threshold and, therefore, there is no current flowing through the system. At this point, the external microprocessor should set ...
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Only a power-down or setting the RESET pin low can reset the 2 ADE7878 to use the I C port. Once locked, the serial port choice is maintained when the ADE7878 changes PSMx power modes. Immediately after entering PSM0, theADE7878 ...
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ADE7878 Table 10. Power Modes and Related Characteristics Power Mode All Registers PSM0 State After Hardware Reset Set to default State After Software Reset Set to default PSM1 Not available PSM2 Not available PSM3 Not available 1 Setting for all ...
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Table 11. Recommended Actions When Changing Power Modes Initial Recommended Actions Power Before Setting Next Mode Power Mode Stop DSP by setting PSM0 Run[15:0] = 0x0000. Disable HSDC by clearing Bit 6 (HSDEN the CONFIG[15:0] register. Mask ...
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ADE7878 THEORY OF OPERATION ANALOG INPUTS The ADE7878 has seven analog inputs forming current and voltage channels. The current channels consist of four pairs of fully differential voltage inputs: IAP and IAN, IBP and IBN, ICP and ICN, and INP ...
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The Σ-Δ converter uses two techniques to achieve high resolu- tion from what is essentially a 1-bit conversion technique. The first is oversampling. Oversampling means that the signal is sampled at a rate (frequency) that is many times higher than ...
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ADE7878 PGA1 BITS REFERENCE GAIN[2:0] ×1, ×2, ×4, ×8, ×16 IAP V PGA1 ADC IN IAN V IN +0.5V/GAIN 0V –0.5V/GAIN ANALOG INPUT RANGE PGA2 BITS GAIN[5:3] ×1, ×2, ×4, ×8, ×16 INP V PGA2 IN INN Current Waveform Gain ...
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Current Channel Sampling The waveform samples of the current channel are taken at the output of HPF and stored into the IAWV, IBWV, ICWV, and INWV 24-bit signed registers at a rate of 8 kSPS. All power and rms calculations ...
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ADE7878 DICOEFF[23:0] 24-bit signed register is accessed as a 32-bit register with four MSBs padded with 0s and sign extended to 28 bits, which practically means it is transmitted equal to 0xFFF8000. When the digital integrator is switched off, the ...
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PGA3 BITS GAIN[8:6] ×1, ×2, ×4, ×8, ×16 VAP V PGA3 +0.5V/GAIN 0V –0.5V/GAIN ANALOG INPUT RANGE CHANGING PHASE VOLTAGE DATAPATH The ADE7878 can direct one phase voltage input to the computa- tional datapath of another ...
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ADE7878 The digital filter has a pole and is clocked at 256 kHz result, there is a phase lag between the analog input signal (one of IA, IB, IC, VA, VB, and VC) and the ...
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In these cases, use the time intervals between phase voltages to analyze the phase sequence (see the Time Interval Between Phases section for details). Figure 42 presents the case ...
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ADE7878 The ANGLE0, ANGLE1, and ANGLE2 registers are 16-bit unsigned registers with 1 LSB corresponding to 3.90625 μs (256 kHz clock), which means a resolution of 0.0703° (360° × 50 Hz/256 kHz) for 50 Hz systems and 0.0843° (360° × ...
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When the Phase B voltage falls below the indicated threshold into the SAGLVL[23:0] register for two line cycles, Bit VSPHASE[1] in the PHSTATUS[15:0] register is set to 1, and Bit VSPHASE[0] is cleared to 0. Simultaneously, Bit 16 (sag) in ...
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ADE7878 register, and Bit 24 (IPPHASE[0]) of the IPEAK[31:0] register is set the end of the period. This bit remains at 1 for the duration of the second PEAKCYC period of four line cycles. The maximum absolute ...
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Overvoltage and Overcurrent Level Set The content of the overvoltage, OVLVL[23:0], and overcurrent, OILVL[23:0], 24-bit unsigned registers is compared to the abso- lute value of the voltage and current channels. The maximum value of these registers is the maximum value ...
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ADE7878 advance in the voltage channel signal path from +61.5 μs to −374.0 μs, respectively. Negative values written to the PHCAL registers represent a time advance whereas positive values represent a time delay. One LSB is equivalent to 0.976 μs ...
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REFERENCE CIRCUIT The nominal reference voltage at the REF 0.075% V. This is the reference voltage used for the ADCs in the ADE7878. The REF pin can be overdriven by an external IN/OUT source, for example, an external 1.2 V ...
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ADE7878 After the LPF and the execution of the square root, the rms value of f(t) is obtained by ∞ ∑ The rms calculation based on this method is simultaneously processed on ...
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Current RMS Offset Compensation The ADE7878 incorporates a current rms offset compensation register for each phase: AIRMSOS[23:0], BIRMSOS[23:0], CIRMSOS[23:0], and NIRMSOS[23:0]. These are 24-bit signed registers and are used to remove offsets in the current rms calculations. An offset can ...
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ADE7878 Voltage Channel RMS Calculation Figure 57 shows the detail of the signal processing chain for the rms calculation on one of the phases of the voltage channel. The voltage channel rms value is processed from the samples used in ...
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Voltage RMS Offset Compensation The ADE7878 incorporates voltage rms offset compensation registers for each phase: AVRMSOS[23:0], BVRMSOS[23:0], and CVRMSOS[23:0]. These are 24-bit signed registers used to remove offsets in the voltage rms calculations. An offset can exist in the rms ...
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ADE7878 AIGAIN IA APHCAL AVGAIN VA If the phase currents and voltages contain only the fundamental component, are in phase (that is φ = γ full-scale ADC inputs, then multiplying them results in an instantaneous power signal that ...
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Fundamental Active Power Calculation The ADE7878 computes the fundamental active power using a proprietary algorithm that requires some initializations function of the frequency of the network and its nominal voltage measured in the voltage channel. Bit 14 (SELFREQ) in the ...
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ADE7878 Bits[8:6] (REVAPC, REVAPB, and REVAPA, respectively) in the STATUS0[31:0] register are set when a sign change occurs in the power selected by Bit 6 (REVAPSEL) in the ACCMODE[7:0] register. Bits[2:0] (CWSIGN, BWSIGN, and AWSIGN, respectively) in the PHSIGN[15:0] register ...
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WTHR[47:0] ACTIVE POWER ACCUMULATION IN DSP DSP GENERATED PULSES 1 DSP PULSE = 1LSB OF WATTHR[47:0] Figure 62. Active Power Accumulation Inside DSP Figure 62 explains this process. The WTHR[47:0] 48-bit signed register contains the threshold introduced by ...
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ADE7878 Energy Accumulation Modes The active power accumulated in each watt-hour accumulation 32-bit register (AWATTHR, BWATTHR, CWATTHR, AFWATTHR, BFWATTHR, and CFWATTHR) depends on the configuration of Bit 5 and Bit 4 (CONSEL bits) in the ACCMODE[7:0] register. The various configurations ...
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IRQ0 pin is set to high again by writing to the STATUS0 register with the corresponding bit set to 1. Because the active power is integrated on an integer number of half-line cycles in this mode, the sinusoidal components are ...
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ADE7878 Table 16 presents the settling time for the fundamental reactive power measurement, which is the time it takes the power to reflect the value at the input of theADE7878. Table 16. Settling Time for Fundamental Reactive Power Input Signals ...
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Table 17. Sign of Reactive Power Calculation 1 Φ Integrator Sign of Reactive Power Between 0 to +90 Off Positive Between − Off Negative Between 0 to +90 On Positive Between − Negative 1 Φ ...
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ADE7878 energy registers, xVARHR (for REHF interrupt) or xFVARHR (for FREHF interrupt), becomes half full. The status bit is cleared and the IRQ0 pin is set to high by writing to the STATUS0 register with the corresponding bit set to ...
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Integration Time Under a Steady Load The discrete time sample period (T) for the accumulation register is 125 μs (8 kHz frequency). With full-scale pure sinusoidal signals on the analog inputs and a 90° phase difference between the voltage and ...
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ADE7878 APPARENT POWER CALCULATION Apparent power is defined as the maximum power that can be delivered to a load. One way to obtain the apparent power is by multiplying the voltage rms value by the current rms value (also called ...
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Apparent Power Gain Calibration The average apparent power result in each phase can be scaled by ±100% by writing to the phase’s VAGAIN 24-bit register (AVAGAIN[23:0], BVAGAIN[23:0], or CVAG AIN[23:0]). The VAGAIN registers are twos complement signed registers and −23 ...
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ADE7878 where the discrete time sample number the sample period. In the ADE7878, the phase apparent powers are accumulated in the AVAHR[31:0], BVAHR[31:0], and CVAHR[31:0] 32-bit signed registers. The apparent energy register content can roll over ...
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The line cycle apparent energy accumulation mode is activated by setting Bit 2 (LVA) in the LCYCMODE[7:0] register. The apparent energy accumulated over an integer number of zero crossings is written to the xVAHR accumulation registers after the number of ...
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ADE7878 The DSP computes the instantaneous values of all phase powers: total active, fundamental active, total reactive, fundamental reactive, and apparent. The process in which the energy is sign accumulated in various xWATTHR, xVARHR, and xVAHR registers has already been ...
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The derivative of wh must be chosen in such a way to obtain a CFxDEN register content greater than 1. If CFxDEN = 1, then the CFx pin stays active low for only 1 μs; therefore, avoid this number. The ...
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ADE7878 When WATTACC[1:0] = 11, the active powers are accumulated in absolute mode. When the powers are negative, they change sign and accumulate together with the positive power. Figure 73 shows how absolute active power accumulation works. Note that in ...
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Sign of Sum-of-Phase Powers in the CFx Datapath The ADE7878 has a sign detection circuitry for the sum of phase powers that are used in the CFx datapath. As seen in the beginning of the Energy-to-Frequency Conversion section, the energy ...
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ADE7878 No Load Detection Based on Fundamental Active and Reactive Powers This no load condition is triggered when the absolute values of both phase fundamental active and reactive powers are less than or equal to APNOLOAD[23:0] and the respective VARNOLOAD[23:0] ...
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CRC is computed on the default values of the registers, giving the result of 0x33666787. Figure 77 shows how the LFSR works. Bits[a represent the bits from the list of registers presented previously in this section. Bit ...
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ADE7878 INTERRUPTS The ADE7878 has two interrupt pins, IRQ0 and IRQ1. Each of the pins is managed by a 32-bit interrupt mask register, MASK0[31:0] and MASK1[31:0], respectively. To enable an interrupt, a bit in the MASKx[31:0] register must be set ...
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IRQx GLOBAL PROGRAM JUMP INTERRUPT TO ISR SEQUENCE MASK Figure 79. Interrupt Management When PHSTATUS, IPEAK, VPEAK, or PHSIGN Registers Is Involved SERIAL INTERFACES The ADE7878 have three serial port interfaces: one fully 2 licensed I C interface, ...
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ADE7878 the address of the ADE7878 followed by the 16-bit address of the target register. The ADE7878 acknowledges every byte received. The address byte is similar to the address byte of a write operation and is equal to 0x70 (see ...
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SPI-Compatible Interface The SPI of the ADE7878 is always a slave of the communication and consists of four pins: SCLK, MOSI, MISO, and SS. The serial clock for a data transfer is applied at the SCLK logic input. This logic ...
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ADE7878 SS SCLK MOSI MISO SS SCLK MOSI HSDC is an interface that is used to send to an external device, usually a microprocessor or a DSP sixteen 32-bit words. The words represent the instantaneous values of the ...
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Table 22. HSDC_CFG Register Bit Location Bit Name Default Value 0 HCLK 0 1 HSIZE 0 2 HGAP 0 4:3 HXFER[1: HSAPOL 0 7:6 00 When HXFER[1:0] is 10, only the instantaneous values of phase powers are transmitted ...
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ADE7878 Table 23. Communication Times for Various HSDC Settings HXFER[1:0] HGAP ...
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SCLK 31 24 HSDATA IAVW (BYTE 3) HSACTIVE Figure 88. HSDC Communication for HSIZE = 1, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0 ADE7878 EVALUATION BOARD An evaluation board built on the ADE7878 configura- tion supports all ...
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ADE7878 REGISTERS LIST Table 24. Registers List Located in DSP Data Memory RAM Register 1 Address Name R/W 0x4380 AIGAIN R/W 0x4381 AVGAIN R/W 0x4382 BIGAIN R/W 0x4383 BVGAIN R/W 0x4384 CIGAIN R/W 0x4385 CVGAIN R/W 0x4386 NIGAIN R/W 0x4387 ...
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Register 1 Address Name R/W 0x4399 BVARGAIN R/W 0x439A BVAROS R/W 0x439B CVARGAIN R/W 0x439C CVAROS R/W 0x439D AFWGAIN R/W 0x439E AFWATTOS R/W 0x439F BFWGAIN R/W 0x43A0 BFWATTOS R/W 0x43A1 CFWGAIN R/W 0x43A2 CFWATTOS R/W 0x43A3 AFVARGAIN R/W 0x43A4 AFVAROS ...
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ADE7878 Register 1 Address Name R/W 0x43AA VATHR0 R/W 0x43AB WTHR1 R/W 0x43AC WTHR0 R/W 0x43AD VARTHR1 R/W 0x43AE VARTHR0 R/W 0x43AF Reserved N/A 4 0x43B0 VANOLOAD R/W 0x43B1 APNOLOAD R/W 0x43B2 VARNOLOAD R/W 0x43B3 VLEVEL R/W Bit Length During ...
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Register 1 Address Name R/W 0x43B4 Reserved N/A 4 0x43B5 DICOEFF R/W 0x43B6 HPFDIS R/W 4 0x43B7 to Reserved N/A 0x43B8 ISUMLVL R/W 0x43BF ISUM R 0x43C0 AIRMS R 0x43C1 AVRMS R 0x43C2 BIRMS R 0x43C3 BVRMS R 0x43C4 CIRMS ...
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ADE7878 Table 25. Internal DSP Memory RAM Registers Bit 1 Address Name R/W Length 0xE203 Reserved R/W 16 0xE228 Run R read and W is write unsigned register and ...
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Bit 1 Address Name R/W Length 0xE505 BIMAV R 20 0xE506 CIMAV R 20 0xE507 OILVL R/W 24 0xE508 OVLVL R/W 24 0xE509 SAGLVL R/W 24 0xE50A MASK0 R/W 32 0xE50B MASK1 R/W 32 0xE50C IAWV R 24 0xE50D IBWV ...
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ADE7878 Bit 1 Address Name R/W Length 0xE600 PHSTATUS R 16 0xE601 ANGLE0 R 16 0xE602 ANGLE1 R 16 0xE603 ANGLE2 R 16 0xE604 to Reserved 0xE606 0xE607 PERIOD R 16 0xE608 PHNOLOAD R 16 0xE609 to Reserved 0xE60B 0xE60C ...
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Bit 1 Address Name R/W Length 0xEC00 LPOILVL R/W 8 0xEC01 CONFIG2 R read and W is write 24- or 20-bit signed or unsigned register that is transmitted as a 32-bit word ...
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ADE7878 Bit Location Bit Name Default Value 7 REVAPB 0 8 REVAPC 0 9 REVPSUM1 0 10 REVRPA 0 11 REVRPB 0 12 REVRPC 0 13 REVPSUM2 0 14 CF1 15 CF2 16 CF3 17 DREADY 0 18 REVPSUM3 0 ...
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Bit Location Bit Name Default Value 5 ZXTOVC 0 6 ZXTOIA 0 7 ZXTOIB 0 8 ZXTOIC 0 9 ZXVA 0 10 ZXVB 0 11 ZXVC 0 12 ZXIA 0 13 ZXIB 0 14 ZXIC 0 15 RSTDONE 1 16 ...
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ADE7878 Bit Location Bit Name Default Value 6 REVAPA 0 7 REVAPB 0 8 REVAPC 0 9 REVPSUM1 0 10 REVRPA 0 11 REVRPB 0 12 REVRPC 0 13 REVPSUM2 0 14 CF1 15 CF2 16 CF3 17 DREADY 0 ...
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Bit Location Bit Name Default Value 7 ZXTOIB 0 8 ZXTOIC 0 9 ZXVA 0 10 ZXVB 0 11 ZXVC 0 12 ZXIA 0 13 ZXIB 0 14 ZXIC 0 15 RSTDONE 0 16 SAG ...
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ADE7878 Bit Location Bit Name Default Value 12 VSPHASE[ VSPHASE[ VSPHASE[ Reserved 0 Table 36. PHNOLOAD Register (Address 0xE608) Bit Location Bit Name Default Value 0 NLPHASE[ NLPHASE[ NLPHASE[2] 0 ...
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Bit Default Location Bit Name Value 7 TERMSEL3[ TERMSEL3[2] 1 10:9 ANGLESEL[1: VNOMAEN 0 12 VNOMBEN 0 13 VNOMCEN 0 14 SELFREQ 0 15 Reserved 0 Table 38. GAIN Register (Address 0xE60F) Bit Bit Name Default ...
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ADE7878 Table 39. CFMODE Register (Address 0xE610) Bit Location Bit Name Default Value 2:0 CF1SEL[2:0] 000 5:3 CF2SEL[2:0] 001 8:6 CF3SEL[2:0] 010 9 CF1DIS 1 10 CF2DIS 1 11 CF3DIS 1 12 CF1LATCH 0 13 CF2LATCH 0 14 CF3LATCH 0 ...
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Table 40. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616) Bit Location Bit Name Default Value 9:0 PHCALVAL 0000000000 15:10 Reserved 000000 Table 41. PHSIGN Register (Address 0xE617) Bit Location Bit Name Default Value 0 AWSIGN 0 1 ...
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ADE7878 Table 42. CONFIG Register (Address 0xE618) Bit Default Location Bit Name value 0 INTEN 0 2:1 Reserved 00 3 SWAP 0 4 MOD1SHORT 0 5 MOD2SHORT 0 6 HSDCEN 0 7 SWRST 0 9:8 VTOIA[1:0] 00 11:10 VTOIB[1:0] 00 ...
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Table 43. MMODE Register (Address 0xE700) Bit Location Bit Name Default Value 1:0 PERSEL[1: PEAKSEL[ PEAKSEL[ PEAKSEL[2] 1 7:5 Reserved 000 Table 44. ACCMODE Register (Address 0xE701) Bit Location Bit Name Default Value 1:0 ...
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ADE7878 Table 45. CONSEL[1:0] Bits in Energy Registers Energy Registers CONSEL[1:0]=00 AWATTHR, AFWATTHR VA × IA BWATTHR, BFWATTHR VB × IB CWATTHR, CFWATTHR VC × IC AVARHR, AFVARHR VA × IA’ BVARHR, BFVARHR VB × IB’ CVARHR, CFVARHR VC ×IC’ ...
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Bit Location Bit Name Default Value 4:3 HXFER[1: HSAPOL 0 7:6 Reserved 00 Table 48. LPOILVL Register (Address 0xEC00) Bit Location Bit Name Default value 2:0 LPOIL[2:0] 111 7:3 LPLINE[4:0] 000 Table 49. CONFIG2 Register (Address 0xEC01) Bit ...
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... ADE7878 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADE7878ACPZ −40°C to +85°C ADE7878ACPZ-RL −40°C to +85° RoHS Compliant Part. 6.10 0.30 6.00 SQ 0.23 5.90 0. 0.50 BSC 21 0.45 20 TOP VIEW BOTTOM VIEW 0.40 ...
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NOTES Rev. 0| Page ADE7878 ...
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ADE7878 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08510-0-2/10(0) Rev. 0| Page ...