S1D13A04F00A Epson Electronics America Inc-Semiconductor Div, S1D13A04F00A Datasheet - Page 45
![IC LCD COMPANION 160KB 128-TQFP](/photos/7/35/73560/s1d13a04f00a_sml.jpg)
S1D13A04F00A
Manufacturer Part Number
S1D13A04F00A
Description
IC LCD COMPANION 160KB 128-TQFP
Manufacturer
Epson Electronics America Inc-Semiconductor Div
Specifications of S1D13A04F00A
Display Type
LCD
Voltage - Supply
1.8 V ~ 2.75 V
Mounting Type
Surface Mount
Package / Case
125-TQFP, 125-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Operating Temperature
-
Interface
-
Configuration
-
Digits Or Characters
-
Other names
S1D13A04F00A100
S1D13A04F00A100
S1D13A04F00A100
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S1D13A04F00A
Manufacturer:
Epson Electronics America Inc-Semiconductor Div
Quantity:
10 000
Company:
Part Number:
S1D13A04F00A1
Manufacturer:
EPSON
Quantity:
816
Part Number:
S1D13A04F00A1
Manufacturer:
EPSON/爱普生
Quantity:
20 000
Company:
Part Number:
S1D13A04F00A100
Manufacturer:
OSRAM
Quantity:
4 600
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Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 2003/05/01
WE#
0
0
0
1
1
1
T
Symbol
f
BUSCLK
BUSCLK
t10
t11
t12
t13
t14
t1
t2
t3
t4
t5
t6
t7
t8
t9
RD#
1
1
1
0
0
0
Bus clock frequency
Bus clock period
A[16:0], M/R#, BHE# setup to first BUSCLK rising edge where CS# =
0 and either RD# = 0 or WE# = 0
CS# setup to BUSCLK rising edge
RD#, WE# setup to BUSCLK rising edge
RD# or WE# state change to WAIT# driven low
RD# falling edge to D[15:0] driven (read cycle)
D[15:0] setup to 4th rising BUSCLK edge after CS#=0 and WE#=0
A[16:0], M/R#, BHE# and CS# hold from RD#, WE# rising edge
CS# deasserted to reasserted
WAIT# rising edge to RD#, WE# rising edge
WE#, RD# deasserted to reasserted
Rising edge of either RD# or WE# to WAIT# high impedance
D[15:0] hold from WE# rising edge (write cycle)
D[15:0] hold from RD# rising edge (read cycle)
Cycle Length
BHE#
0
1
0
0
1
0
Note
Table 6-9: Generic #2 Interface Truth Table for Little Endian
Generic #2 interface only supports Little Endian mode.
A0
0
0
1
0
0
1
D[15:8]
Table 6-8: Generic #2 Interface Timing
valid
valid
valid
valid
Parameter
-
-
D[7:0]
valid
valid
valid
valid
-
-
Revision 6.0
16-bit write
8-bit write at even address
8-bit write at odd address
16-bit read
8-bit read at even address
8-bit read at odd address
1/f
Comments
BUSCLK
Min
9
1
2
1
0
1
6
9
1
0
0
1
2
Max
0.5
50
10
10
X37A-A-001-06
T
T
T
T
S1D13A04
BUSCLK
BUSCLK
BUSCLK
BUSCLK
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 39
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