S1D13A04F00A Epson Electronics America Inc-Semiconductor Div, S1D13A04F00A Datasheet - Page 141

• Manufacturer Part Number: S1D13A04F00A
• Description: IC LCD COMPANION 160KB 128-TQFP
• Manufacturer: Epson Electronics America Inc-Semiconductor Div

Specifications of S1D13A04F00A

• Display Type: LCD
• Voltage - Supply: 1.8 V ~ 2.75 V
• Mounting Type: Surface Mount
• Package / Case: 125-TQFP, 125-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Operating Temperature: -
• Interface: -
• Configuration: -
• Digits Or Characters: -
• Other names: S1D13A04F00A100; S1D13A04F00A100

Epson Research and Development
Vancouver Design Center
8.5 2D Acceleration (BitBLT) Registers (Offset = 8000h)
bit 18
bit 17
bit 16
bit 0
Hardware Functional Specification
Issue Date: 2003/05/01
BitBLT Control Register
REG[8000h]
31
15
30
14
29
13
Default = 00000000h
Note
28
12
These registers control the S1D13A04 2D Acceleration engine. For detailed BitBLT
programming instructions, see the S1D13A04 Programming Notes and Examples,
document number X37A-G-003-xx.
BitBLT Color Format Select
This bit selects the color format that the 2D operation is applied to.
When this bit = 0, 8 bpp (256 color) format is selected.
When this bit = 1, 16 bpp (64K color) format is selected.
BitBLT Destination Linear Select
When this bit = 1, the Destination BitBLT is stored as a contiguous linear block of
memory.
When this bit = 0, the Destination BitBLT is stored as a rectangular region of memory.
The BitBLT Memory Address Offset register (REG[8014h]) determines the address offset
from the start of one line to the next line.
BitBLT Source Linear Select
When this bit = 1, the Source BitBLT is stored as a contiguous linear block of memory.
When this bit = 0, the Source BitBLT is stored as a rectangular region of memory.
The BitBLT Memory Address Offset register (REG[8014h]) determines the address offset
from the start of one line to the next line.
BitBLT Enable
This bit is write only.
Setting this bit to 1 begins the 2D BitBLT operation. This bit must not be set to 0 while a
BitBLT operation is in progress.
To determine the status of a BitBLT operation use the BitBLT Busy Status bit
(REG[8004h] bit 0).
27
11
26
10
n/a
25
9
Revision 6.0
24
n/a
8
23
7
22
6
21
5
20
4
19
3
Format
Select
Color
18
2
Read/Write
X37A-A-001-06
Linear
Select
Dest
17
1
S1D13A04
Page 135
Source
Enable
BitBLT
Linear
Select
(WO)
16
0