S1D13A04F00A Epson Electronics America Inc-Semiconductor Div, S1D13A04F00A Datasheet - Page 279

• Manufacturer Part Number: S1D13A04F00A
• Description: IC LCD COMPANION 160KB 128-TQFP
• Manufacturer: Epson Electronics America Inc-Semiconductor Div

Specifications of S1D13A04F00A

• Display Type: LCD
• Voltage - Supply: 1.8 V ~ 2.75 V
• Mounting Type: Surface Mount
• Package / Case: 125-TQFP, 125-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Operating Temperature: -
• Interface: -
• Configuration: -
• Digits Or Characters: -
• Other names: S1D13A04F00A100; S1D13A04F00A100

Epson Research and Development
Vancouver Design Center
10.4.2 Write to EP4 FIFO Valid bit cleared by NAK
10.4.3 EP3 Interrupt Status bit set by NAKs
Programming Notes and Examples
Issue Date: 2002/08/21
After the local CPU sets EP4 FIFO Valid (in Endpoint 4 FIFO Status Register,
REG[402Ch]), the S1D13A04 will erroneously clear the EP4 valid bit if the S1D13A04 is
concurrently sending a NAK handshake in response to a previous IN token to EP4.
Work Around
The work-around is in the ‘EP4 Packet Transmitted’ interrupt routine. It requires the
interrupt routine to know whether the recently queued packet was a zero-length packet or
not, so that must be stored as a bit when the packet was loaded into the FIFO. On entry to
the ‘EP4 Packet Transmitted’ interrupt routine:
For a non-zero-length Packet
Check the FIFO count. If it is non-zero, this error occurred. In that case, set FIFO Valid
again, clear the interrupt status bit, and exit the interrupt routine.
For a zero-length Packet
Check the Software EOT bit (in Control Register, REG[4000h]). If it is set, the FIFO Valid
write failed. In that case, set FIFO Valid again, clear the interrupt status bit, and exit the
interrupt routine
When receiving Bulk OUT packets from a Host PC, the S1D13A04 “Endpoint 3 Interrupt
Status” interrupt typically is used to notify the peripheral firmware that a packet has been
received. This bit also serves as the “Receive FIFO Valid” bit, so additional packets
addressed to Endpoint 3 are NAKed until this status bit is cleared. Once cleared, however,
it may become set by another packet which is NAKed by the S1D13A04, causing the
Receive FIFO to become “Valid” again. The Host PC may immediately attempt to re-
transmit the NAKed packet. The firmware should be written to prevent a cycle in which the
FIFO is “Valid” each time that the Host PC sends an OUT packet.
The following rules govern the S1D13A04’s behavior regarding packets received on
Endpoint 3:
Rule A. At the end of a received OUT token to EP3 (and before the data is received), the
S1D13A04 decides to NAK the packet if the “EP3 Interrupt Status” bit is set, and will
therefore throw away data received.
Rule B. At the end of a received packet (including one which is NAKed), the S1D13A04
sets the “EP3 Interrupt Status” bit.
Rule C. Local firmware should clear the “EP3 Interrupt Status” bit after reading all bytes
out of the EP3 Receive FIFO.
X37A-G-003-05
S1D13A04
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