SG6742HRSY Fairchild Semiconductor, SG6742HRSY Datasheet - Page 9

• Manufacturer Part Number: SG6742HRSY
• Description: IC CTRLR PWM PROG GREEN CM 8SOP
• Manufacturer: Fairchild Semiconductor

Specifications of SG6742HRSY

• Output Isolation: Isolated
• Frequency Range: 90 ~ 110kHz
• Voltage - Input: 9.5 ~ 30 V
• Voltage - Output: 18V
• Power (watts): 400mW
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Number Of Outputs: 1
• Duty Cycle (max): 70 %
• Output Voltage: 18 V
• Mounting Style: SMD/SMT
• Switching Frequency: 110 KHz
• Operating Supply Voltage: 30 V
• Supply Current: 2.7 mA
• Maximum Operating Temperature: + 105 C
• Fall Time: 50 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 250 ns
• Synchronous Pin: No
• Topology: Flyback Converter
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

© 2008 Fairchild Semiconductor Corporation
SG6742HL/HR • Rev. 1.0.4
Functional Description
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor through an external diode and resistor,
R
current drawn from pin HV is 2.3mA and charges the
hold-up capacitor through the diode and resistor. When
the V
current switches off. At this moment, the V
only supplies the SG6742HL/HR to keep the V
the auxiliary winding of the main transformer to provide
the operating current.
Operating Current
Operating current is around 2.7mA. The low operating
current enables better efficiency and reduces the
requirement of V
Green-Mode Operation
The proprietary green-mode function provides an off-
time modulation to reduce the switching frequency in
the light-load and no-load conditions. The on time is
limited for better abnormal or brownout protection. V
which is derived from the voltage feedback loop, is
taken as the reference. Once V
threshold voltage, switching frequency is continuously
decreased to the minimum green-mode frequency of
around 22KHz.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current sense signal and V
When the voltage on SENSE pin reaches around
V
immediately. V
voltage around 0.85V for output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 15.5V and 9.5V. During startup, the hold-up capacitor
must be charged to 15.5V through the startup resistor to
enable the IC. The hold-up capacitor continues to
supply V
auxiliary winding of the main transformer. V
drop below 9.5V during this startup process. This UVLO
hysteresis window ensures that hold-up capacitor is
adequate to supply V
COMP
HV
, (1N4007 / 100KΩ recommended). Typical startup
=(V
DD
DD
FB
capacitor level reaches V
–0.6)/4,
before the energy can be delivered from
COMP
DD
hold-up capacitance.
is internally clamped to a variable
DD
a
during startup.
switch
FB
, the feedback voltage.
cycle
FB
DD-ON
is lower than the
is
, the startup
DD
DD
terminated
capacitor
DD
must not
before
FB
,
9
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 6ms soft-start
circuit significantly reduces the startup current spike
and output voltage overshoot.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability
SG6742HL/HR inserts a synchronized positive-going
ramp at every switching cycle.
Constant Output Power Limit
When the SENSE voltage, across the sense resistor
R
output GATE drive is turned off after a small delay, t
This delay introduces an additional current proportional
to t
regardless of the input voltage V
results in a larger additional current and the output
power limit is higher than under low input line voltage.
To compensate this variation for wide AC input range, a
sawtooth power-limiter is designed to solve the unequal
power-limit problem. The power limiter is designed as a
positive ramp signal fed to the inverting input of the
OCP comparator. This results in a lower current limit at
high-line inputs than at low-line inputs.
V
V
damage due to abnormal conditions. If the V
is over the over-voltage protection voltage (V
lasts for t
the V
again. Over-voltage conditions are usually caused by
open feedback loops.
DD
S
DD
, reaches the threshold voltage, around 1V, the
PD
over-voltage protection has been built in to prevent
Over-Voltage Protection (OVP)
DD
• V
voltage drops below the UVLO, then starts
D-VDDOVP
and
IN
/ L
P
prevents
. Since the delay is nearly constant
, the PWM pulses are disabled until
sub-harmonic
IN
, higher input voltage
www.fairchildsemi.com
DD-OVP
oscillation.
DD
voltage
) and
PD
.