EPC4QI100 Altera, EPC4QI100 Datasheet - Page 80

IC CONFIG DEVICE 4MBIT 100-PQFP

EPC4QI100

Manufacturer Part Number
EPC4QI100
Description
IC CONFIG DEVICE 4MBIT 100-PQFP
Manufacturer
Altera
Series
EPCr
Datasheet

Specifications of EPC4QI100

Programmable Type
In System Programmable
Memory Size
4Mb
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-MQFP, 100-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2189

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPC4QI100
Manufacturer:
ALTERA
Quantity:
1
Part Number:
EPC4QI100
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPC4QI100
Manufacturer:
TI
Quantity:
3
Part Number:
EPC4QI100
Manufacturer:
ALTERA
0
Part Number:
EPC4QI100
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPC4QI100N
Manufacturer:
ALTERA
Quantity:
300
Part Number:
EPC4QI100N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPC4QI100N
Manufacturer:
ALTERA
0
Part Number:
EPC4QI100N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
3–28
Figure 3–19. Read Operation Timing
Configuration Handbook (Complete Two-Volume Set)
    
f
1
DCLK
DATA
ASDI
nCS
Add_Bit 0
Figure 3–19
operation.
Table 3–17
operation.
Table 3–17. Read Operation Parameters
Existing batches of EPCS1 and EPCS4 manufactured on 0.15 µm process geometry
support AS configuration up to 40 MHz. However, batches of EPCS1 and EPCS4
manufactured on 0.18 µm process geometry support only up to 20 MHz. EPCS16,
EPCS64, and EPCS128 are not affected.
For information about product traceability and transition date to differentiate
between 0.15 µm process geometry and 0.18 µm process geometry EPCS1 and EPCS4,
refer tothe Process Change Notification
Family.
f
t
t
t
t
RCLK
CH
CL
ODIS
nCLK2D
Symbol
t
nCLK2D
defines the serial configuration device timing parameters for read
Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
Bit N
shows the timing waveform for the serial configuration device's read
Read clock frequency (from FPGA or
embedded processor) for read bytes
operation
DCLK high time
DCLK low time
Output disable time after read
Clock falling edge to data
Bit N 1
Parameter
PCN 0514: Manufacturing Changes on EPCS
t
CL
t
CH
Min
Bit 0
25
25
© December 2009
t
ODIS
Max
15
20
8
Timing Information
Altera Corporation
MHz
Unit
ns
ns
ns
ns

Related parts for EPC4QI100