EPC4QC100N Altera, EPC4QC100N Datasheet - Page 17

• Manufacturer Part Number: EPC4QC100N
• Description: IC CONFIG DEVICE 4MBIT 100-PQFP
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC4QC100N

• Programmable Type: In System Programmable
• Memory Size: 4Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-MQFP, 100-PQFP
• Memory Type: Flash
• Clock Frequency: 66.7MHz
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: QFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C To +70°C
• Access Time: 90ns
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1378; EPC4QC100N

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
Functional Description
Dynamic Configuration (Page Mode)
© December 2009 Altera Corporation
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The dynamic configuration (or page mode) feature allows the enhanced configuration
device to store up to eight different sets of designs for all the FPGAs in your system.
You can then choose which page (set of configuration files) the enhanced
configuration device should use for FPGA configuration.
Dynamic configuration or the page mode feature enables you to store a minimum of
two pages: a factory default or fail-safe configuration, and an application
configuration. The fail-safe configuration page could be programmed during system
production, while the application configuration page could support remote or local
updates. These remote updates could add or enhance system features and
performance. However, with remote update capabilities comes the risk of possible
corruption of configuration data. In the event of such a corruption, the system could
automatically switch to the fail-safe configuration and avoid system downtime.
The enhanced configuration device page mode feature works with the Stratix Remote
System Configuration feature, to enable intelligent remote updates to your systems.
For more information about remotely updating Stratix FPGAs, refer to
Configuration with Stratix & Stratix GX Devices
The three PGM[2..0] input pins control which page is used for configuration, and
these pins are sampled at the start of each configuration cycle when OE goes high. The
page mode selection allows you to dynamically reconfigure the functionality of your
FPGA by switching the PGM[2..0] pins and asserting nCONFIG. Page 0 is defined as
the default page and the PGM[2] pin is the most significant bit (MSB).
The PGM[2..0] input pins must not be left floating on your board, regardless of
whether this feature is used or not. When this feature is not used, connect the
PGM[2..0] pins to GND to select the default page 000.
The enhanced configuration device pages are dynamically sized regions in memory.
The start address and length of each page is programmed into the option-bit space of
the flash memory during initial programming. All subsequent configuration cycles
will sample the PGM[] pins and use the option-bit information to jump to the start of
the corresponding configuration page. Each page must have configuration files for all
FPGAs in your system that are connected to that enhanced configuration device.
For example, if your system requires three configuration pages and includes two
FPGAs, each page will store two SRAM Object Files (.sof) for a total of six .sof in the
configuration device.
Furthermore, all enhanced configuration device configuration schemes (PS, FPP, and
concurrent PS) are supported with the page-mode feature. The number of pages,
devices, or both, that can be configured using a single enhanced configuration device
is only limited by the size of the flash memory.
For detailed information about the page-mode feature implementation and
programming file generation steps using the Quartus II software, refer to the
Enhanced Configuration Devices
chapter in volume 2 of the Configuration Handbook.
in the Stratix Device Handbook.
Configuration Handbook (Complete Two-Volume Set)
Remote System
Altera
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