EPC4QC100N Altera, EPC4QC100N Datasheet - Page 15

• Manufacturer Part Number: EPC4QC100N
• Description: IC CONFIG DEVICE 4MBIT 100-PQFP
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC4QC100N

• Programmable Type: In System Programmable
• Memory Size: 4Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-MQFP, 100-PQFP
• Memory Type: Flash
• Clock Frequency: 66.7MHz
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: QFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C To +70°C
• Access Time: 90ns
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1378; EPC4QC100N

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
Functional Description
Figure 1–4. FPP Configuration with External Flash Interface
Notes to
(1) For external flash interface support in EPC8 enhanced configuration device, contact Altera Applications.
(2) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should be left floating. These pins
(3) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15 to F-A15, C-A16 to
(4) For PORSEL, PGM[], and EXCLK pin connections, refer to
(5) RY/BY# pin is only available for Sharp flash-based EPC8 and EPC16.
(6) To protect Intel Flash based EPC devices content, isolate the V
Intel-Flash-Based EPC Device Protection
© December 2009 Altera Corporation
should not be connected to any signal; they are no-connect pins.
F-A16, and BYTE# to V
C-RP# to F-RP#, C-WE# to F-WE#, TM1 to V
Device Protection” on page
Figure
1–4:
N.C.
n
Figure 1–4
use.
In the absence of the lock bit protection feature in the EPC4, EPC8, and EPC16 devices
with Intel flash, Altera recommends four methods to protect the Intel Flash content in
EPC4, EPC8, and EPC16 devices. Any method alone is sufficient to protect the flash.
The methods are listed here in the order of descending protection level:
1. Using an RP# of less than 0.3 V on power-up and power-down for a minimum of
MSEL
nCEO
CC
. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages:
1–15.
100 ns to a maximum 25 ms disables all control pins, making it impossible for a
write to occur.
APEX II Device
Stratix Series
CONF_DONE
or
DATA[7..0]
nCONFIG
nSTATUS
shows an FPP configuration schematic with the external flash interface in
DCLK
nCE
CC
V
, TM0 to GND, and WP# to V
CC
GND
V
CC
Table
CCW
GND
supply from V
1–10.
V
(Note 1)
CC
Enhanced Configuration
WP#
BYTE# (3)
TM1
WE#C
RP#C
DCLK
DATA[7..0]
OE
nCS
nINIT_CONF
C-A0 (3)
C-A1 (3)
C-A15 (3)
C-A16 (3)
TMO
CC
Device
CC
.
. For more information, refer section
RY/BY# (5)
A[20..0] (2)
PGM[2..0]
DQ[15..0]
PORSEL
EXCLK
VCCW
WE#F
A0-F
A1-F
A15-F
A16-F
RP#F
OE#
CE#
Configuration Handbook (Complete Two-Volume Set)
V
CC
(4)
(4)
(4)
(4)
(4)
(6)
PLD or Processor
WE#
RP#
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
“Intel-Flash-Based EPC
1–15