RC28F128K3C115 Intel, RC28F128K3C115 Datasheet - Page 70

• Manufacturer Part Number: RC28F128K3C115
• Description: IC FLASH 128MBIT 115NS 64BGA
• Manufacturer: Intel

Specifications of RC28F128K3C115

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 128M (8Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 848521

28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Appendix C Flowcharts
70
Figure 25. Write to Buffer Flowchart
Yes
Read Status Register
Issue Write to Buffer
Write Confirm 0xD0
Write Word Count,
and Block Address
Command 0xE8 and
(at Block Address)
Write Buffer Data,
Check if Desired
Supports Buffer
Set Time-out or
Target Address
Read Extended
Status Register
Block Address
Block Address
Loop Counter
Start Address
Another Write
Programming
Available?
Full Status
to Buffer?
Complete
Get Next
SR.7 = ?
Is Buffer
XSR.7 =
Writes?
Device
X = N?
X = 0
Start
1 = Yes
Yes
Yes
No
1
No
0 = No
No
0
Write to Buffer Aborted
Write Buffer Data,
Use Single Word
Write to another
Block Address
Block Address
Programming
Abort Write
to Buffer?
X = X + 1
Time-out
Expired?
or Count
No
No
Yes
Register Command
Issue Read Status
Yes
sequences complete. Write 0xFF after the last operation to reset
1. Word count values on DQ
register. Count ranges for this device are N = 0x00 to 0x1F.
2. The device outputs the status register when read (XSR is no
longer available).
3. Write Buffer contents will be programmed at the device start
address or destination flash address.
4. Align the start address on a Write Buffer boundary for
maximum programming performance (i.e., A
address = 0).
5. The device aborts the Write to Buffer command if the current
address is outside the original block address.
6. The Status register indicates an "improper command
sequence" if the Write to Buffer command is aborted. Follow
this with a Clear Status Register command.
Full status check can be done after all erase and write
the device to read array mode.
(Notes 1, 2)
(Notes 3, 4)
(Notes 5, 6)
Operation
Standby
Standby
Write
Read
Write
Write
Write
Write
Read
Bus
Command
Write to
Confirm
Buffer
Write
7
-DQ
Addr = Block Address
XSR.7 = Valid
Addr = Block Address
Check XSR.7
1 = Write Buffer available
0 = No Write Buffer available
Data = N = W ord Count
N = 0 corresponds to count = 1
Addr = Block Address
Data = Write Buffer Data
Addr = Start Address
Data = Write Buffer Data
Addr = Block Address
Addr = Block Address
Status register Data
Transition to V
OE# updates SR
Addr = Block Address
Check SR.7
1 = WSM Ready
0 = WSM Busy
Data = 0xE8
Data = 0xD0
0
are loaded into the Count
Comments
5
IL
–A
of either CE# or
1
of the start
Datasheet