RC28F128K3C115 Intel, RC28F128K3C115 Datasheet - Page 33

• Manufacturer Part Number: RC28F128K3C115
• Description: IC FLASH 128MBIT 115NS 64BGA
• Manufacturer: Intel

Specifications of RC28F128K3C115

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 128M (8Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 848521

8.0
8.1
8.2
8.3
Datasheet
Power and Reset
This section provides an overview of some system level considerations in regards to the flash
device. This section provides a brief description of power-up, power-down, decoupling and reset
design considerations.
Power-Up/Down Characteristics
In order to prevent any condition that may result in a spurious write or erase operation, it is
recommended to power-up and power-down V
power-up V
before V
Power Supply Decoupling
When the device is enabled, many internal conditions change. Circuits are energized, charge pumps
are switched on, and internal voltage nodes are ramped. All of this internal activities produce
transient signals. The magnitude of the transient signals depends on the device and system loading.
To minimize the effect of these transient signals, a 0.1 µF ceramic capacitor is required across each
V
connections.
Additionally, for every eight flash devices, a 4.7 µF electrolytic capacitor should be placed between
V
slumps caused by PCB (print circuit board) trace inductance.
Reset Characteristics
By holding the flash device in reset during power-up and power-down transitions, invalid bus
conditions may be masked. The flash device enters reset mode when RST# is driven low. In reset,
internal flash circuitry is disabled and outputs are placed in a high-impedance state. After return
from reset, a certain amount of time is required before the flash device is able to perform normal
operations. After return from reset, the flash device defaults to asynchronous page mode. If RST#
is driven low during a program or erase operation, the program or erase operation will be aborted
and the memory contents at the aborted block or address are no longer valid. See
Operation Waveforms” on page 34
CC
CC
/V
and V
SS
CC
and V
SS
.
PEN
at the power supply connection. This 4.7 µF capacitor should help overcome voltage
CCQ
with or slightly after V
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
/V
SSQ
signal
. Capacitors should be placed as close as possible to device
for detailed information regarding reset timings.
CC
. Conversely, V
CC
and V
CCQ
PEN
together. It is also recommended to
must power down with or slightly
Figure 19, “Reset
33