RC28F128K3C115 Intel, RC28F128K3C115 Datasheet - Page 39

• Manufacturer Part Number: RC28F128K3C115
• Description: IC FLASH 128MBIT 115NS 64BGA
• Manufacturer: Intel

Specifications of RC28F128K3C115

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 128M (8Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 848521

10.0
10.1
Datasheet
Note: Asynchronous page mode reads can only be performed when RCR bit 15 is set (default). (See
Read Modes
The device supports four types of read modes: read array, read identifier, read status or read query.
Upon power-up or return from reset, the device defaults to read array mode. To change the device’s
read mode, the appropriate Read command must be written to the device. (See
Commands” on page
status, read ID, and CFI query modes.
The device supports two types of array read modes: asynchronous page mode and synchronous
burst mode. Asynchronous page mode is the default read mode after powered-up, or after a reset.
The RCR must be configured to enable Synchronous Burst reads of the flash memory array. (See
Section 10.3, “Read Configuration Register” on page
The Read Array command functions independent of V
array mode operations in detail.
Asynchronous Page-Mode Read
Asynchronous page mode is the default read mode upon power-up or return from reset. However,
to perform array reads after any other device operation (e.g., a write operation), the Read Array
command must be issued in order to read from the flash memory. Asynchronous page-mode reads
are permitted in all blocks, and it is used to access device register information.
Section 10.3, “Read Configuration Register” on page
To perform an asynchronous page-mode read, an address is driven onto A[A
and OE# are asserted. WE# and RST# must be de-asserted. ADV# must be held low throughout the
read cycle. CLK and WAIT are not used for asynchronous page-mode reads. If only asynchronous
reads are to be performed, it is recommended that CLK be tied to a valid V
driven out on D[15:0] after a minimum delay. (See
In asynchronous page mode, one of 16 eight-word groups are “sensed” simultaneously from the
flash memory and loaded into an internal page buffer. After the initial access delay, the first word
out of the data buffer corresponds to the initial address, A[A
A[A
+2:A
Address bits A[A
data buffer at any given time. Subsequent reads from the device come from the page buffer, and are
output on D[15:0] after a minimum delay, as long as address bits A[A
address bits that change. Data can be read from the page buffer multiple times, and in any order. If
address bits A[A
load a new eight-word group from the flash memory into the page buffer.
By controlling certain signals, such as CE# and/or OE#, the device can be made to output less than
eight-words of data. Asynchronous page-mode read is used to access register information, but only
one word is loaded into the page buffer.
MAX
MIN
:A
], are not latched.
MIN
+ 3] are latched by the device. However, the lower address bits, A[A
MAX
MIN
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
+2:A
37.) See
:A
MIN
MIN
+3] change at any time, or if CE# is toggled, the device will sense and
Section 14.0, “Special Modes” on page 56
] determine which word of the eight-word group is output from the
Section 7.1, “Read Operations” on page
40.)
40.)
PEN
. The following sections describes read-
MAX
:A
MIN
MIN
]. Address bits
for details regarding read
+2:A
IH
MAX
level. Array data is
Section 9.2, “Device
MIN
:A
] are the only
MIN
MIN
], and CE#
24.)
39