IDT71V432S5PF IDT, Integrated Device Technology Inc, IDT71V432S5PF Datasheet

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IDT71V432S5PF

Manufacturer Part Number
IDT71V432S5PF
Description
IC SRAM 1MBIT 5NS 100TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT71V432S5PF

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
1M (32K x 32)
Speed
5ns
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.63 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
71V432S5PF

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Price
Part Number:
IDT71V432S5PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71V432S5PF8
Manufacturer:
IDT, Integrated Device Technology Inc
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Part Number:
IDT71V432S5PFG
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IDT, Integrated Device Technology Inc
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IDT71V432S5PFG8
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IDT
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83
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IDT71V432S5PFG8
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IDT, Integrated Device Technology Inc
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10 000
Part Number:
IDT71V432S5PFGI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Pin Description Summary
CacheRAM is a trademark of Integrated Device Technology.
Pentium processor is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
©2005 Integrated Device Technology, Inc.
Features
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Description
organized as 32K x 32 with full support of the Pentium™ and PowerPC™
I/O
A
CE
CS
OE
GW
BWE
BW
CLK
ADV
ADSC
ADSP
LBO
ZZ
V
V
0
DD
SS
32K x 32 memory configuration
Supports high-performance system speed:
Commercial and Industrial:
— 5ns Clock-to-Data Access (100MHz)
— 6ns Clock-to-Data Access (83MHz)
— 7ns Clock-to-Data Access (66MHz)
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC32K32D7LG-XX)
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Operates with a single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
The IDT71V432 is a 3.3V high-speed 1,048,576-bit CacheRAM
–A
0
0
1,
–I/O
, CS
14
BW
31
1
2,
BW
3,
BW
4
Chip Enable
Chips Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Linear / Interleaved Burst Order
Sleep Mode
Data Input/Output
Ground
Address Inputs
Address Status (Cache Controller)
Address Status (Processor)
3.3V Power
32K x 32 CacheRAM™
3.3V Synchronous SRAM
Burst Counter
Single Cycle Deselect
1
processor interfaces. The pipelined burst architecture provides cost-
effective 3-1-1-1 secondary cache performance for processors up to
100 MHz.
control registers. Internal logic allows the CacheRAM to generate a self-
timed write based upon a decision which can be left until the extreme end
of the write cycle.
system designer, as the IDT71V432 can provide four cycles of data for
a single address presented to the CacheRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses will be defined by the internal burst counter
and the LBO input pin.
volume 3.3V CMOS process, and is packaged in a JEDEC Standard
14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board
density in both desktop and notebook applications.
The IDT71V432 CacheRAM contains write, data, address, and
The burst mode feature offers the highest level of performance to the
The IDT71V432 CacheRAM utilizes IDT's high-performance, high-
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Power
Ground
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
DC
DC
OCTOBER 2008
IDT71V432
DSC-3104/06
3104 tbl 01

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IDT71V432S5PF Summary of contents

Page 1

... Features ◆ ◆ ◆ ◆ ◆ 32K x 32 memory configuration ◆ ◆ ◆ ◆ ◆ Supports high-performance system speed: Commercial and Industrial: — 5ns Clock-to-Data Access (100MHz) — 6ns Clock-to-Data Access (83MHz) — 7ns Clock-to-Data Access (66MHz) ◆ ◆ ◆ ◆ ◆ ...

Page 2

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Pin Definitions (1) Symbol Pin Function A –A Address Inputs 0 14 ADSC Address Status (Cache Controller) ADSP Address Status (Processor) ADV Burst Address Advance BWE ...

Page 3

... Write Register Byte 3 Write Register Byte 4 Write Register Q D Enable Register CLK Enable Delay Register 32 6.42 3 INTERNAL ADDRESS 32K BIT MEMORY ARRAY – Byte 1 Write Driver 8 Byte 2 Write Driver 8 Byte 3 Write Driver 8 Byte 4 Write Driver 8 OUTPUT REGISTER DATA INPUT REGISTER OUTPUT ...

Page 4

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Absolute Maximum Ratings Symbol Rating (2) Terminal Voltage with V TERM Respect to GND (3) V Terminal Voltage with TERM Respect to GND T Operating Temperature ...

Page 5

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Pin Configuration 100 I I ...

Page 6

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Synchronous Truth Table Address Operation Used Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None ...

Page 7

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Synchronous Write Function Truth Table GW Operation Read H Read H Write all Bytes L Write all Bytes H (2) Write Byte 1 H (2) Write ...

Page 8

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter |I | Input Leakage Current LI ZZ and LBO Input Leakage Current |I ...

Page 9

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect AC Electrical Characteristics (V = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges) DD Symbol Parameter CLOCK PARAMETERS t Clock Cycle Time CYC (1) t Clock High ...

Page 10

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Timing Waveform of Pipelined Read Cycle Commercial and Industrial Temperature Ranges (1,2) 6.42 10 ...

Page 11

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Timing Waveform of Combined Pipelined Read and Write Cycles Commercial and Industrial Temperature Ranges 6.42 11 (1,2,3) ...

Page 12

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No. 1 — GW Controlled Commercial and Industrial Temperature Ranges 6.42 12 (1,2,3) . ...

Page 13

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No. 2 — Byte Controlled Commercial and Industrial Temperature Ranges 6.42 13 (1,2,3) ...

Page 14

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Timing Waveform of Sleep (ZZ) and Power-Down Modes Commercial and Industrial Temperature Ranges (1,2,3) 6.42 14 ...

Page 15

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Non-Burst Read Cycle Timing Waveform CLK ADSP or ADSC ADDRESS Av DATA OUT NOTES: 1. ZZ, CE and OE are LOW for this cycle. ...

Page 16

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect 100-pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline Commercial and Industrial Temperature Ranges 6.42 16 ...

Page 17

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Ordering Information 71V432 S X Device Power Speed Type PART NUMBER SPEED IN MEGAHERTZ 71V432S5PF 71V432S6PF 71V432S7PF Process/ Package Temperature Range t PARAMETER ...

Page 18

IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Datasheet Document History 9/10/99 Pg. 3–5 Pg. 5 Pg. 11–14 Pg. 17 03/09/00 Pg 04/04/00 Pg. 16 08/09/00 08/17/01 03/31/05 Pg.17 ...

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