IDT71P72604S167BQ IDT, Integrated Device Technology Inc, IDT71P72604S167BQ Datasheet - Page 14

• Manufacturer Part Number: IDT71P72604S167BQ
• Description: IC SRAM 18MBIT 167MHZ 165FBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT71P72604S167BQ

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 71P72604S167BQ

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
cess Port (TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during
manufacturing and system diagnostics. In conformance with IEEE 1149.1,
the SRAM contains a TAP controller, Instruction register, Bypass Regis-
ter and ID register. The TAP controller has a standard 16-state machine
that resets internally upon power-up; therefore, the TRST signal is not
JTAG Block Diagram
TAP Controller State Diagram
71P72804 (1M x 18-Bit) 71P72604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 2
This part contains an IEEE standard 1149.1 Compatible Test Ac-
S
TDI
TMS
TCK
A,D
K,K
C,C
Q
CQ
CQ
1
0
Test Logic Reset
Run Test Idle
0
1
1
1
1
Identification Reg.
Instruction Reg .
Capture DR
Update DR
Select DR
Pause DR
BYPASS Reg.
Control Signal s
TAP Controller
Exit 1 DR
Exit 2 DR
Shift DR
0
SRAM
CORE
0
1
0
1
1
0
1
0
0
0
6109 drw 18
1
1
Capture IR
Update IR
Select IR
Pause IR
Exit 1 IR
Exit 2 IR
Shift IR
0
0
1
1
0
1
1
6109 drw 17
TDO
1
0
0
0
0
6.42
14
required. It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfacing with normal operation of the
SRAM, TCK must be tied to V
TDI are designed so an undriven input will produce a response identical
to the application of a logic 1, and may be left unconnected, but they may
also be tied to V
NOTES:
1. Places Qs in Hi-Z in order to sample all input data regardless of other
2. TDI is sampled as an input to the first ID register to allow for the serial
3. Bypass register is initialized to Vss when BYPASS instruction is in
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
JTAG Instruction Coding
IR2
0
0
0
0
exiting the Shift DR states.
1
1
1
1
shift of the external TDI data.
SRAM inputs.
voked. The Bypass Register also holds serially loaded TDI when
IR1
0
0
0
0
1
1
1
1
IR0
0
0
0
0
1
1
1
1
DD
Commercial and IndustrialTemperature Range
SAMPLE/PRELOAD Boundary Scan register
through a resistor. TDO should be left unconnected.
RESERVED
RESERVED
RESERVED
Instruction
SAMPLE-Z
BYPASS
EXTEST
IDCODE
SS
to preclude a mid level input. TMS and
Boundary Scan Register
Identification register
Boundary Scan Register
Do Not Use
Do Not Use
Do Not Use
Bypass Register
TDO Output
6109tbl 13
Notes
2
5
4
5
5
3
1