CY7C1381D-133BGXC Cypress Semiconductor Corp, CY7C1381D-133BGXC Datasheet - Page 7

• Manufacturer Part Number: CY7C1381D-133BGXC
• Description: IC SRAM 18MBIT 133MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381D-133BGXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05544 Rev. *A
Pin Definitions
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
The CY7C1381D/CY7C1383D supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BW
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE
V
TDO
TDI
TMS
TCK
NC
V
SSQ
SS
/DNU
E
) and Byte Write Select (BWX) inputs. A Global Write
Name
CDV
JTAG serial output
Synchronous
JTAG serial input
JTAG serial input
) is 6.5 ns (133-MHz device).
(continued)
Synchronous
Synchronous
Ground/DNU
I/O Ground
JTAG-
Clock
I/O
–
1
is HIGH.
1
, CE
Ground for the I/O circuitry.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not being utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be left floating or connected to V
resistor. This pin is not available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to V
No Connects. Not internally connected to the die. 36M, 72M, 144M and 288M are address
expansion pins are not internally connected to the die.
This pin can be connected to Ground or should be left floating.
1
, CE
2
, and CE
2
, CE
®
3
[2]
3
PRELIMINARY
and i486
[2]
) and an
are all
SS
. This pin is not available on TQFP packages.
1
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BW
cycle. If the write inputs are asserted active ( see Write Cycle
Descriptions table for appropriate states that indicate a write)
on the next clock rise,the appropriate data will be latched and
written into the device.Byte writes are allowed. All I/Os are
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ
written into the specified address location. Byte writes are
allowed. All I/Os are tri-stated when a write is detected, even
a byte write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1381D/CY7C1383D provides an on-chip two-bit
wraparound burst counter inside the SRAM. The burst counter
is fed by A
burst order. The burst order is determined by the state of the
MODE input. A LOW on MODE will select a linear burst
sequence. A HIGH on MODE will select an interleaved burst
Description
[1:0]
, and can follow either a linear or interleaved
E
, and BW
X
)are ignored during this first clock
1
, CE
1
, CE
2
, and CE
2
DD
, CE
DD
through a pull up
CY7C1381D
CY7C1383D
. This pin is not
3
[2]
3
[2]
are all asserted
are all asserted
Page 7 of 29
[A:D]
will be
X
)