CY7C1381D-133BGXC Cypress Semiconductor Corp, CY7C1381D-133BGXC Datasheet - Page 10

• Manufacturer Part Number: CY7C1381D-133BGXC
• Description: IC SRAM 18MBIT 133MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1381D-133BGXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05544 Rev. *A
Truth Table for Read/Write
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1381D/CY7C1383D incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
The CY7C1381D/CY7C1383D contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V
nally pulled up and may be unconnected. They may alternately
be connected to V
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
Read
Read
Write Byte A – ( DQ
Write Byte B – ( DQ
Write All Bytes
Write All Bytes
SS
) to prevent clocking of the device. TDI and TMS are inter-
Function (CY7C1383D)
DD
A
B
through a pull-up resistor. TDO should be
and DQP
and DQP
A
B
)
)
[3,8]
PRELIMINARY
GW
H
H
H
H
H
L
TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
1
0
TEST-LOGIC
RUN-TEST/
RESET
IDLE
0
BWE
H
X
L
L
L
L
1
1
0
CAPTURE-DR
UPDATE-DR
PAUSE-DR
DR-SCAN
SHIFT-DR
EXIT1-DR
EXIT2-DR
1
SELECT
0
0
1
0
1
1
BW
0
X
H
H
X
L
L
B
1
1
0
0
CY7C1381D
CY7C1383D
1
0
CAPTURE-IR
Page 10 of 29
UPDATE-IR
PAUSE-IR
1
IR-SCAN
SHIFT-IR
EXIT1-IR
EXIT2-IR
SELECT
0
0
1
0
1
1
BW
0
H
H
X
X
L
L
A
1
1
0
0