CY7C1381D-133BGXC Cypress Semiconductor Corp, CY7C1381D-133BGXC Datasheet - Page 21

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CY7C1381D-133BGXC

Manufacturer Part Number
CY7C1381D-133BGXC
Description
IC SRAM 18MBIT 133MHZ 165LFBGA
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1381D-133BGXC

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
18M (512K x 36)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
165-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1381D-133BGXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-05544 Rev. *A
Switching Characteristics
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes:
18. Tested initially and after any design or process change that may affect these parameters.
19. This part has a voltage regulator internally; t
20. t
21. At any given voltage and temperature, t
ADS
ADVS
WES
DS
CES
AH
ADH
WEH
ADVH
DH
CEH
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
Data Input Set-up Before CLK Rise
Chip Enable Set-up
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
GW , BWE , BW
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
OEHZ
Over the Operating Range (continued)
POWER
is less than t
[A:D]
[A:D]
Description
is the time that the power needs to be supplied above V
Hold After CLK Rise
Set-up Before CLK Rise
OELZ
PRELIMINARY
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
[20, 21]
Min.
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
133 MHz
DD
Max.
( minimum) initially, before a read or write operation
Min.
1.5
1.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
100 MHz
CY7C1381D
CY7C1383D
Max.
Page 21 of 29
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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