PSD813F1A-90UI STMicroelectronics, PSD813F1A-90UI Datasheet - Page 11

• Manufacturer Part Number: PSD813F1A-90UI
• Description: IC FLASH 1MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD813F1A-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1980

Pin Name
PC0
PC1
PC2
PC3
PC4
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
28
27
25
24
23
22
21
7
6
5
4
3
2
52
51
20
19
18
17
14
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
These pins make up Port A. These port pins are configurable and can have the following
functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellAB0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 5).
5. Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA
in burst mode.
6. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
7. D0/A16-D3/A19 in M37702M2 mode.
8. Peripheral I/O mode.
Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
PA4-PA7 can be configured as CMOS or Open Drain Outputs.
These pins make up Port B. These port pins are configurable and can have the following
functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 5).
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However,
PB4-PB7 can be configured as CMOS or Open Drain Outputs.
PC0 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC0) output.
3. Input to the PLDs.
4. TMS Input
This pin can be configured as a CMOS or Open Drain output.
PC1 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC1) output.
3. Input to the PLDs.
4. TCK Input
This pin can be configured as a CMOS or Open Drain output.
PC2 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC2) output.
3. Input to the PLDs.
This pin can be configured as a CMOS or Open Drain output.
PC3 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC3) output.
3. Input to the PLDs.
4. TSTAT output
5. Ready/Busy output for In-System parallel programming.
This pin can be configured as a CMOS or Open Drain output.
PC4 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC4) output.
3. Input to the PLDs.
4. TERR output
This pin can be configured as a CMOS or Open Drain output.
2
2
for the JTAG Interface.
for the JTAG Interface.
2
2
for the JTAG Interface.
for the JTAG Serial Interface.
Description
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