PSD813F1A-90MI STMicroelectronics, PSD813F1A-90MI Datasheet - Page 65

• Manufacturer Part Number: PSD813F1A-90MI
• Description: IC FLASH 1MBIT 90NS 52QFP
• Manufacturer: STMicroelectronics

Specifications of PSD813F1A-90MI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1978

Automatic Power-down (APD) Unit and Power-down Mode
The APD Unit, shown in Figure 33, puts the PSD
into Power-down mode by monitoring the activity
of Address Strobe (ALE/AS, PD0). If the APD Unit
is enabled, as soon as activity on Address Strobe
(ALE/AS, PD0) stops, a four bit counter starts
counting. If Address Strobe (ALE/AS, PD0) re-
mains inactive for fifteen clock periods of CLKIN
(PD1), the Power-down (PDN) signal becomes ac-
tive, and the PSD enters Power-down mode, as
discussed next.
Power-down Mode
By default, if you enable the PSD APD unit, Power
Down Mode is automatically enabled. The device
will enter Power Down Mode if the address strobe
(ALE/AS) remains inactive for fifteen CLKIN (pin
PD1) clock periods.
The following should be kept in mind when the
PSD is in Power Down Mode:
–
–
–
Figure 33. APD Unit
Table 29. PSD Timing and Standby Current during Power-down Mode
Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit.
Power-down
If the address strobe starts pulsing again, the
PSD will return to normal operation. The PSD
will also return to normal operation if either the
CSI input returns low or the Reset input
returns high.
The MCU address/data bus is blocked from all
memories and PLDs.
Various signals can be blocked (prior to Power
Down Mode) from entering the PLDs by
Mode
2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is 0.
PLD Propagation
Normal t
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
Delay
PD
DISABLE
FLASH/EEPROM/SRAM
(1)
TRANSITION
DETECTION
DETECT
EDGE
Access Time
No Access
Memory
CLR
COUNTER
APD
Access Recovery Time
PD
PD
to Normal Access
–
–
Table 28. Power-down Mode’s Effect on Ports
MCU I/O
PLD Out
Address Out
Data Port
Peripheral I/O
DISABLE BUS
INTERFACE
setting the appropriate bits in the PMMR
registers. The blocked signals include MCU
control signals and the common clock
(CLKIN). Note that blocking CLKIN from the
PLDs will not block CLKIN from the APD unit.
All PSD memories enter standby mode and
are drawing standby current. However, the
PLDs and I/O ports do not go into standby
mode because you don’t want to have to wait
for the logic and I/O to “wake-up” before their
outputs can change. See Table
Down Mode effects on PSD ports.
Typical standby current are of the order of the
microampere (see Table 29). These standby
current values assume that there are no
transitions on any PLD input.
t
LVDV
Port Function
PLD
EEPROM SELECT
FLASH SELECT
POWER DOWN
( PDN )
SRAM SELECT
SELECT
Typical Standby Current
5V V
50µA
No Change
No Change
Undefined
Tri-State
Tri-State
CC
(2)
AI02891
Pin Level
PSD813F1A
28
3V V
25µA
for Power
CC
(2)
65/111