CY7C1329-100AC Cypress Semiconductor Corp, CY7C1329-100AC Datasheet - Page 8

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CY7C1329-100AC

Manufacturer Part Number
CY7C1329-100AC
Description
IC SRAM 2MBIT 100MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1329-100AC

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
2M (64K x 32)
Speed
100MHz
Interface
Parallel
Voltage - Supply
3.15 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1090

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Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1329-100AC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C1329-100AC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CY7C1329-100ACT
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Quantity:
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Part Number:
CY7C1329-100ACT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document #: 38-05279 Rev. *A
AC Test Loads and Waveforms
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
Parameter
10. Input waveform should have a slew rate of 1V/ns.
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
12. t
13. At any given voltage and temperature, t
CYC
CH
CL
AS
AH
CO
DOH
ADS
ADH
WES
WEH
ADVS
ADVH
DS
DH
CES
CEH
CHZ
CLZ
EOHZ
EOLZ
EOV
OUTPUT
loading of the specified I
steady-state voltage.
CHZ
, t
CLZ
, t
EOV
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWE, GW, BW[3:0] Set-up Before CLK Rise
BWE, GW, BW[3:0] Hold After CLK Rise
ADV Set-up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-up Before CLK Rise
Data Input Hold After CLK Rise
Chip Select Set-up
Chip Select Hold After CLK Rise
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
OE LOW to Output Valid
Z
, t
0
EOLZ
= 50
, and t
(a)
OL
/I
V
OH
EOHZ
L
= 1.5V
and load capacitance. Shown in (a) and (b) of AC Test Loads.
[12]
[12]
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
R
L
Over the Operating Range
Description
= 50
EOHZ
[12]
is less than t
[12, 13]
[12, 13]
OUTPUT
INCLUDING
3.3V
JIG AND
SCOPE
EOLZ
5 pF
and t
CHZ
[11,12,13]
is less than t
(b)
R = 317
R = 351
Min.
7.5
1.9
1.9
1.5
0.5
1.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
CLZ
0
0
.
-133
GND
3.3V
Max.
4.2
3.5
3.5
4.2
< 3.3 ns
10%
Min.
3.2
3.2
2.5
0.5
2.0
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
1.5
10
0
0
ALL INPUT PULSES
-100
90%
Max.
5.0
5.5
5.0
5
(c)
Min.
13.3
5.0
5.0
2.5
0.5
2.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2
0
0
CY7C1329
-75
[10]
200 mV from
90%
Max.
Page 8 of 15
7.0
6
6
6
10%
< 3.3 ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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