CY7C1329-100AC Cypress Semiconductor Corp, CY7C1329-100AC Datasheet - Page 3

• Manufacturer Part Number: CY7C1329-100AC
• Description: IC SRAM 2MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1329-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 2M (64K x 32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1090

Document #: 38-05279 Rev. *A
Pin Definitions
49–44, 81,82,
99, 100,
32–37
96–93
88
87
89
98
97
92
86
83
84
85
64
29, 28,
25–22, 19,
18,13,12,
9–6, 3, 2, 79,
78, 75–72,
69, 68, 63, 62
59–56, 53, 52
15, 41, 65, 91 V
17, 40, 67, 90 V
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 21, 26,
55, 60, 71, 76
31
1, 14, 16, 30,
38, 39, 42, 43,
50, 51, 66, 80
Pin Number
A
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQ
V
V
MODE
NC
Name
[15:0]
DD
SS
DDQ
SSQ
1
2
3
[31:0]
[3:0]
Asynchronous
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-Clock
I/O Ground
I/O Power
Ground
Supply
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
I/O-
I/O
–
Address Inputs used to select one of the 64K address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE
CE
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes
to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
of CLK, a global Write is conducted (ALL bytes are written, regardless of the values
on BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a Byte Write.
Clock input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
Output Enable, asynchronous input, active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first
clock of a Read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When
asserted LOW, A
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE
Address Strobe from Controller, sampled on the rising edge of CLK. When
asserted LOW, A
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical
“sleep” condition with data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A
Read cycle. The direction of the pins is controlled by OE. When OE is asserted
LOW, the pins behave as outputs. When HIGH, DQ
condition.
Power supply inputs to the core of the device. Should be connected to 3.3V
power supply.
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
Ground for the I/O circuitry. Should be connected to ground of the system.
Selects burst order. When tied to GND selects linear burst sequence. When tied
to V
should remain static during device operation.
No Connects.
3
1
DDQ
are sampled active. A
is HIGH.
[3:0]
or left floating selects interleaved burst sequence. This is a strap pin and
and BWE).
[15:0]
[15:0]
2
1
1
and CE
and CE
and CE
is captured in the address registers. A
is captured in the address registers. A
[1:0]
2
3
3
to select/deselect the device.
feed the 2-bit counter.
to select/deselect the device. ADSP is ignored if
to select/deselect the device.
Description
[15:0]
1
is deasserted HIGH.
during the previous clock rise of the
[31:0]
are placed in a three-state
[1:0]
[1:0]
CY7C1329
are also loaded
are also loaded
1
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, CE
2
, and