CY7C1329-100AC Cypress Semiconductor Corp, CY7C1329-100AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1329-100AC
• Description: IC SRAM 2MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1329-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 2M (64K x 32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1090

Document #: 38-05279 Rev. *A
Linear Burst Sequence
ZZ Mode Electrical Characteristics
Cycle Descriptions
I
t
t
A
00
01
10
11
DDZZ
ZZS
ZZREC
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “sleep”
Notes:
Parameter
1.
2.
3.
[1:0]
Address
Next Cycle
First
X = “Don't Care,” 1 = HIGH, 0 = LOW.
Write is defined by BWE, BW
The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
Snooze mode standby
current
Device operation to ZZ
ZZ recovery time
A
01
10
11
00
[1:0]
Address
Second
External
External
Current
Current
None
None
None
None
None
None
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
External
Next
Next
Add. Used
Description
[1,2,3]
[3:0]
, and GW. See Write Cycle Descriptions table.
A
10
11
00
01
[1:0]
Address
Third
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Test Conditions
ZZ > V
ZZ > V
CE
X
1
X
1
X
0
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
A
11
00
01
10
ZZ < 0.2V
3
[1:0]
Address
Fourth
DD
DD
CE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
0.2V
0.2V
2
CE
X
X
X
X
X
X
X
X
1
0
0
0
0
0
0
1
1
1
1
1
0
1
1
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.
1
2t
Min.
ADSP
CYC
X
X
X
X
X
X
1
X
1
X
X
0
0
1
1
0
1
1
1
1
1
1
1
ADSC
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
X
1
, CE
2t
ADV
Max.
2
X
X
X
X
X
X
X
X
X
CYC
0
0
0
0
1
1
1
1
1
1
0
0
1
1
3
, CE
3,
ZZREC
ADSP, and ADSC must
OE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
CY7C1329
after the ZZ input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Page 5 of 15
Unit
mA
ns
ns
X
X
X
X
X
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Write