MT47H64M8B6-25E L:D TR Micron Technology Inc, MT47H64M8B6-25E L:D TR Datasheet - Page 23

• Manufacturer Part Number: MT47H64M8B6-25E L:D TR
• Description: IC DDR2 SDRAM 512MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M8B6-25E L:D TR

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 64Mx8
• Density: 512Mb
• Address Bus: 16b
• Access Time (max): 400ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 205mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1427-2

Electrical Specifications – I
I
Table 8: General I
I
Table 9: I
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. O 7/09 EN
I
CL (I
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Speed Grade
Timing patterns for 4-bank x4/x8/x16 devices
-5E
-37E
-3
-3E
-25
-25E
-187E
DD
DD7
DD
RCD (I
RC (I
RRD (I
RRD (I
CK (I
RAS MIN (I
RAS MAX (I
RP (I
RFC (I
RFC (I
RFC (I
RFC (I
FAW (I
FAW (I
Parameters
DD
Specifications and Conditions
DD
DD
DD
Conditions
DD
DD
DD
DD
)
DD
DD
DD
DD
DD
)
)
)
)
) - x4/x8 (1KB)
) - x16 (2KB)
- 256Mb)
- 512Mb)
- 1Gb)
- 2Gb)
) - x4/x8 (1KB)
) - x16 (2KB)
DD7
DD
DD
)
)
Timing Patterns (4-Bank Interleave READ Operation)
I
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D
DD7
DD
Notes:
Parameters
Timing Patterns
The detailed timings are shown below for I
conflict with pattern requirements of Table 9, then Table 9 requirements take precedence.
1. A = active; RA = read auto precharge; D = deselect.
2. All banks are being interleaved at
3. Control and address bus inputs are stable during DESELECTs.
70,000
127.5
-25E
12.5
57.5
12.5
105
195
7.5
2.5
10
45
75
5
DD
Parameters
70,000
127.5
105
195
-25
7.5
2.5
15
60
10
45
15
75
6
23
Defined by pattern in Table 9
Defined by pattern in Table 9
Electrical Specifications – I
70,000
127.5
105
195
-3E
7.5
12
57
10
45
12
75
t
4
3
RC (I
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DD
DD7
512Mb: x4, x8, x16 DDR2 SDRAM
) without violating
. Where general I
70,000
127.5
105
195
7.5
15
60
10
45
15
75
-3
5
3
70,000
127.5
-37E
3.75
105
195
7.5
15
60
10
45
15
75
4
©2004 Micron Technology, Inc. All rights reserved.
t
DD
RRD (I
parameters in Table 8
DD
DD
70,000
127.5
105
195
-5E
7.5
) using a BL = 4.
15
55
10
40
15
75
3
5
Parameters
Units
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns