MT47H256M4HQ-187E:E TR Micron Technology Inc, MT47H256M4HQ-187E:E TR Datasheet - Page 110

• Manufacturer Part Number: MT47H256M4HQ-187E:E TR
• Description: IC DDR2 SDRAM 1GBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H256M4HQ-187E:E TR

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 1.875ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 256Mx4
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 350ps
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 190mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1426-2

Figure 65: WRITE – DM Operation
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
DQS, DQS#
Bank select
Command
Address
CK#
CKE
A10
DQ 7
DM
CK
NOP 1
T0
Notes:
Bank x
ACT
RA
RA
T1
t CK
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. BL = 4, AL = 1, and WL = 2 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T11.
5.
6. Subsequent rising DQS signals must align to the clock within
7. DI n = data-in for column n; subsequent elements are applied in the programmed order.
8.
9.
NOP 1
T2
these times.
t
t
t
t CH
WR starts at the end of the data burst regardless of the data mask condition.
DSH is applicable during
DSS is applicable during
t RCD
t CL
Bank x
WRITE 2
Col n
3
T3
AL = 1
NOP 1
T4
WL ± t DQSS (NOM)
WL = 2
NOP 1
t
T5
110
t
DQSS (MAX) and is referenced from CK T7 or T8.
DQSS (MIN) and is referenced from CK T6 or T7.
t WPRE
NOP 1
T6
DI
n
t RAS
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T6n
t DQSL t DQSH t WPST
NOP 1
6
T7
1Gb: x4, x8, x16 DDR2 SDRAM
T7n
NOP 1
T8
Transitioning Data
NOP 1
© 2004 Micron Technology, Inc. All rights reserved.
T9
t
DQSS.
t WR 5
T10
NOP 1
One bank
All banks
Don’t Care
Bank x 4
T11
PRE
WRITE
t RPA