MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 10
![IC DDR3 SDRAM 1GBIT 78FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT41J256M4HX-15E:D TR
Manufacturer Part Number
MT41J256M4HX-15E:D TR
Description
IC DDR3 SDRAM 1GBIT 78FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J256M4HX-15E:D TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (256M x 4)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-FBGA
Organization
256Mx4
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
220mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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State Diagram
Figure 2:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. F 11/08 EN
Power
applied
ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
From any
state
Power
on
Simplified State Diagram
RESET
procedure
Reset
WRITE
CKE L
Initialization
calibration
WRITE AP
Writing
power-
Writing
Active
down
PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
ZQCL
ZQ
ZQCL/ZQCS
WRITE
PDX
PDE
PRE, PREA
10
WRITE AP
WRITE AP
WRITE
Precharging
MRS, MPR,
Activating
MRS
leveling
PRE, PREA
active
write
Bank
Idle
ACT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
READ
READ AP
READ AP
PRE, PREA
PDE
1Gb: x4, x8, x16 DDR3 SDRAM
PDX
READ
SRX
SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
REF
Precharge
SRE
Reading
Reading
READ AP
power-
down
©2006 Micron Technology, Inc. All rights reserved.
CKE L
READ
State Diagram
Refreshing
refresh
Self
Automatic
sequence
Command
sequence
CKE L
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