MT46H8M16LFCF-75 Micron Technology Inc, MT46H8M16LFCF-75 Datasheet - Page 12

• Manufacturer Part Number: MT46H8M16LFCF-75
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M16LFCF-75

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Operating Mode
Extended Mode Register
Temperature Compensated Self Refresh
Partial Array Self Refresh
Output Driver Strength
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
The normal operating mode is selected by issuing a LOAD MODE REGISTER SET
command with bits A7–A11 each set to zero, and bits A0–A6 set to the desired values.
All other combinations of values for A7–A11 are reserved for future use and/or test
modes. Test modes and reserved states should not be used because unknown operation
or incompatibility with future versions may result.
The extended mode register controls functions specific to low power operation. These
additional functions include drive strength, temperature compensated self refresh, and
partial array self refresh.
On this version of the Mobile DDR SDRAM, a temperature sensor is implemented for
automatic control of the self refresh oscillator on the device. Programming of the
temperature compensated self refresh (TCSR) bits will have no effect on the device. The
self refresh oscillator will continue refresh at the factory programmed optimal rate for
the device temperature.
For further power savings during SELF REFRESH, the PASR feature allows the controller
to select the amount of memory that will be refreshed during SELF REFRESH. The
refresh options are as follows:
• Full array: banks 0, 1, 2, and 3
• Half array: banks 0 and 1
• Quarter array: bank 0
WRITE and READ commands can still occur during standard operation, but only the
selected banks will be refreshed during SELF REFRESH. Data in banks that are disabled
will be lost.
Because the Mobile DDR SDRAM is designed for use in smaller systems that are mostly
point to point, an option to control the drive strength of the output buffers is available.
Drive strength should be selected based on the expected loading of the memory bus. Bits
A5 and A6 of the extended mode register can be used to select the driver strength of the
DQ outputs. There are three allowable settings for the output drivers (25 ohm internal
impedance, 55 ohm internal impedance, and 80 ohm internal impedance).
12
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Register Definition