IDT70V3579S5BCI8 IDT, Integrated Device Technology Inc, IDT70V3579S5BCI8 Datasheet - Page 11

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IDT70V3579S5BCI8

Manufacturer Part Number
IDT70V3579S5BCI8
Description
IC SRAM 1.125MBIT 5NS 256BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT70V3579S5BCI8

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
1.125M (32K x 36)
Speed
5ns
Interface
Parallel
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
70V3579S5BCI8

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT70V3579S5BCI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Timing Waveform of Read Cycle for Pipelined Operation
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = V
3. The output is disabled (High-Impedance state) by CE
4. Addresses do not have to be accessed sequentially since ADS = V
5. If BE
Timing Waveform of a Multi-Device Pipelined Read
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3579 for this waveform,
2. BE
IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM
ADDRESS
ADDRESS
and are setup for depth expansion in this example. ADDRESS
are for reference use only.
DATA
DATA
ADDRESS
n
DATA
, OE, and ADS = V
n
was HIGH, then the appropriate Byte of DATA
CE
CE
BE
OUT(B1)
OUT(B2)
IL
CLK
R/
CE
CE
(0-3)
OUT
CLK
0(B1)
0(B2)
OE
, CNTEN and CNTRST = V
(B1)
(B2)
W
0
1
(4)
(1)
IL
; CE
t
t
t
t
t
t
t
t
SC
SC
SA
SA
SW
SA
SC
SB
An
1(B1)
A
A
0
0
t
t
t
t
t
HC
HC
t
t
t
HA
HA
HW
HC
HB
HA
, CE
t
CH2
(1 Latency)
t
1(B2)
CH2
IH
t
CYC2
.
, R/W, CNTEN, and CNTRST = V
t
CL2
t
CYC2
A
A
t
CKLZ
1
1
OUT
t
CL2
0
for Qn + 2 would be disabled (High-Impedance state).
(1)
t
An + 1
CD2
= V
IH
(B1)
, CE
= ADDRESS
t
t
1
t
SC
SC
CD2
= V
Q
A
A
IL
2
0
2
IL
t
t
constantly loads the address on the rising edge of the CLK; numbers
t
HC
DC
HC
IH
, BE
.
t
(B2)
CD2
n
6.42
11
= V
in this situation.
IH
following the next rising edge of the clock. Refer to Truth Table 1.
t
An + 2
SB
(5)
Qn
Q
A
A
3
3
1
t
t
t
HB
DC
t
CKHZ
CKLZ
t
DC
t
CD2
Industrial and Commercial Temperature Ranges
Qn + 1
A
A
Q
4
4
2
(1,2)
t
t
t
OHZ
CKHZ
CKLZ
t
t
An + 3
SC
CD2
(3)
t
HC
(2)
t
t
OE
OLZ
A
A
Q
5
5
3
t
t
CKHZ
CKLZ
t
Qn + 2
CD2
4830 drw 06
4830 drw 07
(5)
A
A
Q
6
6
4

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