IDT70V3579S5BCI8 IDT, Integrated Device Technology Inc, IDT70V3579S5BCI8 Datasheet

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IDT70V3579S5BCI8

Manufacturer Part Number
IDT70V3579S5BCI8
Description
IC SRAM 1.125MBIT 5NS 256BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT70V3579S5BCI8

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
1.125M (32K x 36)
Speed
5ns
Interface
Parallel
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
70V3579S5BCI8

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT70V3579S5BCI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Features:
Functional Block Diagram
©2008 Integrated Device Technology, Inc.
CE
CE
OE
R/W
0L
1L
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
L
L
BE
BE
BE
BE
address inputs @ 133MHz
3L
2L
0L
1L
CLK
L
I/O
CNTRST
CNTEN
0L
- I/O
ADS
A
14L
A
0L
35L
L
L
L
Counter/
Address
Reg.
HIGH-SPEED 3.3V 32K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Din_L
ADDR_L
B
W
0
L
MEMORY
B
W
1
L
32K x 36
ARRAY
B
W
2
L
B
W
3
L
1
B
W
3
R
Dout18-26_R
Dout27-35_R
B
W
2
R
Dout9-17_R
Dout0-8_R
B
W
1
R
ADDR_R
B
W
0
R
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 208-pin Plastic Quad Flatpack (PQFP) and
208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid
Array
Green parts available, see ordering information
Din_R
Counter/
Address
Reg.
OCTOBER 2008
IDT70V3579S
BE
BE
BE
BE
3R
2R
1R
0R
I/O
A
A
ADS
CNTEN
CNTRST
CE
R/W
CE
OE
14R
0R
4830 tbl 01
0R
0R
1R
R
R
R
- I/O
R
DSC 4830/16
R
35R
CLK
R
,

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IDT70V3579S5BCI8 Summary of contents

Page 1

... Features: True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 4.2/5/6ns (max.) – Industrial: 5ns (max) Pipelined output mode Counter enable and reset features Dual chip enables allow for depth expansion without ...

Page 2

... High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Description: The IDT70V3579 is a high-speed 32K x 36 bit synchronous Dual- Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times ...

Page 3

IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Pin Configuration (1,2,3,4) 12/12/ I 18L I/O I 18R ...

Page 4

IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Pin Configuration (1,2,3,4) 12/12/01 1 I/O 19L 2 I/O 19R 3 I/O 20L 4 I/O 20R V 5 DDQL I/O 21L I/O 8 21R 9 I/O ...

Page 5

IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Pin Names Left Port Right Port Chip Enables , , R/W R/W Read/Write Enable Output Enable L R ...

Page 6

... External Address Blocked—Counter disabled (Ap reused) I/O ( (p+1) Counter Enabled—Internal Address generation I/O , BEn and OE and BEn , the rising edge of CLK, regardless of all other memory control signals including CE IL Recommended DC Operating Conditions with V (1) Symbol GND 3.3V 150mV V DDQ + 0V 3.3V ...

Page 7

IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM (1) Capacitance (T = +25° 1.0MH ) PQFP ONLY A Z Symbol Parameter Conditions C Input Capacitance IN (3) C Output Capacitance V OUT NOTES: 1. These parameters ...

Page 8

IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating DD L Current (Both Outputs Disabled, Ports Active) ( ...

Page 9

IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM AC Test Conditions (V Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 50Ω DATA OUT Figure ...

Page 10

IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing 3.3V ± 150mV 0°C to +70° Symbol Parameter t Clock Cycle ...

Page 11

IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Read Cycle for Pipelined Operation t CYC2 t CH2 CLK (0- ...

Page 12

... CNTEN, and CNTRST = Addresses do not have to be accessed sequentially since ADS = V are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. NO MATCH (3) t CD2 . IH for the Left Port, which is being written to. ...

Page 13

IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled) t CYC2 t t CH2 CL2 CLK ...

Page 14

IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Timing Waveform of Write with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS (3) INTERNAL (7) An ADDRESS t t SAD HAD ...

Page 15

... LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asyn- chronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. A HIGH LOW on CE for one clock cycle will power 0 1 down the internal circuitry to reduce static power consumption ...

Page 16

IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Ordering Information XXXXX Device Power Speed Package Type NOTE: 1. Contact your local sales office for Industrial temp range in other speeds, packages and powers. 2. Green ...

Page 17

IDT70V3579S High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Datasheet Document History (cont'd) 4/10/01: Added Industrial Temperature Ranges and removed related notes 7/19/01: Page 3 Replaced incorrect BGA package drawing 12/12/01: Page 2, 3 & 4 Added date revision ...

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