M27C801-100B1 STMicroelectronics, M27C801-100B1 Datasheet - Page 9

IC OTP 8MBIT 100NS 32DIP

M27C801-100B1

Manufacturer Part Number
M27C801-100B1
Description
IC OTP 8MBIT 100NS 32DIP
Manufacturer
STMicroelectronics
Datasheets

Specifications of M27C801-100B1

Format - Memory
EPROMs
Memory Type
OTP EPROM
Memory Size
8M (1M x 8)
Speed
100ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
32-DIP (0.600", 15.24mm)
Organization
1Mx8
Interface Type
Parallel
In System Programmable
External
Access Time (max)
100ns
Package Type
PDIP
Reprogramming Technique
OTP
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
50mA
Pin Count
32
Mounting
Through Hole
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Capacitance, Input
6 pF
Capacitance, Output
12 pF
Current, Input, Leakage
±10 μA
Current, Operating
35 mA
Current, Output, Leakage
±10
Current, Supply
35 mA (Max.)
Density
8M
Temperature, Operating
0 to +70 °C
Temperature, Operating, Maximum
70 °C
Temperature, Operating, Minimum
0 °C
Time, Access
100 ns
Time, Fall
≤20 ns
Time, Rise
≤20 ns
Voltage, Input, High
6 V
Voltage, Input, High Level
2 V (Min.)
Voltage, Input, Low
0.8 V
Voltage, Input, Low Level
0.80 V (Max.)
Voltage, Output, High
3.6 V (TTL), 4.3 V (CMOS)
Voltage, Output, Low
0.4 V
Voltage, Supply
5 V
Access Time
45ns
Low Power Consumption
- Active current 35mA at 5 MHz - Standby current 100 μA
Programming Voltage
12.75 V ± 0.25 V
Memory Configuration
1M X 8
Supply Voltage Range
4.5V To 5V
Memory Case Style
DIP
No. Of Pins
32
Rohs Compliant
Yes
Operating Temperature Range
0°C To +70°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-1687-5

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Figure 7. Programming and Verify Modes AC Waveforms
Figure 8. Programming Flowchart
YES
NO
FAIL
= 25
++n
A0-A19
Q0-Q7
V CC
GV PP
E
V CC = 6.25V, V PP = 12.75V
RESET MARGIN MODE
SET MARGIN MODE
CHECK ALL BYTES
NO
2nd: V CC = 4.2V
1st: V CC = 6V
E = 50 s Pulse
VERIFY
n = 0
Addr
Last
YES
YES
NO
tVCHEL
tVPHEL
tQVEL
tAVEL
++ Addr
DATA IN
AI01271B
PROGRAM
VALID
tELEH
tEHQX
PRESTO IIB Programming Algorithm
PRESTO IIB Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 52.5 seconds. This can
be achieved with STMicroelectronics M27C801
due to several design innovations to improve pro-
gramming efficiency and to provide adequate mar-
gin for reliability. Before starting the programming
the internal MARGIN MODE circuit is set in order
to guarantee that each cell is programmed with
enough margin. Then a sequence of 50µs pro-
gram pulses are applied to each byte until a cor-
rect verify occurs. No overprogram pulses are
applied since the verify in MARGIN MODE pro-
vides the necessary margin.
Program Inhibit
Programming of multiple M27C801s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including GV
allel M27C801 may be common. A TTL low level
pulse applied to a M27C801's E input, with V
12.75V, will program that M27C801. A high level E
input inhibits the other M27C801s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at V
falling edge of E.
tEHVPX
IL
. Data should be verified with t
tVPLEL
VERIFY
tELQV
DATA OUT
tEHAX
tEHQZ
AI01270
ELQV
PP
M27C801
of the par-
after the
PP
9/16
at

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